| Deliverable | Projected Date * |
| C.1 | Layout Generator for Leafcell Layout with Compatibility to Third Layer Metal |
| C.1 [1,2] | Source Code (alpha) | 6 |
| C.1 [3] | Source Code (beta) | 12 |
| C.1 [3] | Source Code rev 1.0 | 18 |
| C.1 [4] | Portable Source Code rev 2.0 | 36 |
| C.2 | CMOS standard cell library |
| C.2.1 [1] | Fixed HP standard cell library development | 12 |
| C.2.1 [2] | Fixed HP standard cell library characterization | 15 |
| C.2.1 [3] | Parameterized HP standard cell library and characterization | 24 |
| C.2.2 [1,2] | MSU standard cell library and characterization | 18 |
| C.2.2 [3] | Parameterized MSU standard cell library and characterization | 30 |
| C.2.3 [1,2] | Data path cell library and characterization | 21 |
| C.2.3 [3] | Parameterized Datapath library characterization | 24 |
| C.2.4 [1,2] | Bipolar library and characterization | 18 |
| C.2.4 [3] | BiCMOS I/O cell library and characterization | 36 |
| C.3 | CAD Tool Interfaces |
| C.3 [1,2] | Metal3 with Lager and Mentor | 12 |
| C.3 [3] | Metal3 with Cadence | 24 |
| C.3 [4] | Metal3 Datapath cells with lager, Mentor and Cadence | 36 |
| C.4 | Constraint Driven Design Methodology |
| C.4 [1] | Parameterization methodology | 12 |
| C.4 [2] | Optimization system | 24 |
| C.4 [3] | Methodology demonstration using HYPER synthesis system | 36 |