J. Bibliography

  1. Lakshmi P. Narayana, Automating the Characterization of Standard Cells for Macro-Models Used in Even Driven Simulators," M.S. Thesis, Mississippi State University, May 1993.
  2. S. Chakravarty, X. He, and S. S. Ravi, Minimum Area Layouts of Series-Parallel Transistor Networks is NP-Hard," IEEE Transactions on Computer-Aided Design, vol. 10, number 7, p.p., 943-949, July 1991.
  3. T. Uehara and W. M. Cleemput, Optimal Layout of CMOS Functional Arrays," IEEE Transactions on Computers, vol. C-30, p.p., 305-312, May 1981.
  4. R. Nair, A. Bruss and J. Reif, Linear time Algorithms for Optimal CMOS VLSI: Algorithms and Architectures" (P. Bertolazzi and F. Luccio edition), Amsterdam, Elsevier North-Holland, p.p., 327-338, 1985.
  5. J. Madsen, A New Approach to Optimal Cell Synthesis," IEEE International Conference on Computer-Aided Design, p.p., 336-339, Nov. 1989.
  6. C. Ong, J. Li and C. Lo, GENAC: An Automatic Cell Synthesis Tool," Proceedings 26th Design Automation Conference, p.p., 239-244, June 1989.
  7. R. L. Maziasz and J. P. Hayes, Layout Minimization of CMOS Cells, Kluwer Academic Publishers, Boston MA, 1992.
  8. A. Weinberger, Large Scale Integration of MOS Complex Logic," IEEE Journal of Solid State Circuits, vol. SC-2, p.p., 182-190, Dec. 1967.
  9. C. T. McMullen and R. H. J. M. Otten, Layout Compilation of Linear Transistor Arrays," Proceedings IEEE International Symposium on Circuits and Systems, vol. CAD-9, p.p., 5-7, July 1985.
  10. J. H Kim et al., Palace: a layout generator for SCVS logic blocks," Proceedings 27th Design Automation Conference, p.p., 468-473, June 1990.
  11. H. Y. Chen and S. M. Kang, Performance drive cell generator for dynamic CMOS circuits," Proceedings IEEE International Symposium on Circuits and Systems, p.p., 1883-1886, May 1989.
  12. R. Muller and T. Lengauer, Linear-time Algorithms for two CMOS Layout Problems", VLSI: Algorithms and Architectures, Springer-Verlag, New York, vol. 227, p.p., 121-132, 1985.
  13. D. D. Gajski, Silicon Compilation Addision-Wesley, Reading MA, 1985.
  14. C. Gary and L. Lesniak, Graphs and Digraphs, 2nd ed., Wadsworth & Brooks/Cole Advanced Books & Software, California, p.p., 52-60.
  15. Y. Kwon and C. Kyung, A Fast Heuristic for optimal CMOS Functional Cell Layout Generation," Proceedings IEEE International Symposium on Circuits and Systems, p.p., 2423-2426, May 1989.
  16. C-Y. Hwang, Y-C. Hsieh, Y-L. Lin, and Y-C. Hsu, An Optimal Transistor-Chaining Algorithm for CMOS Cell Layout," IEEE International Conference on Computer-Aided Design, p.p., 344-347, Nov. 1989.
  17. C. Ong, J. Li and C. Lo, GENAC: An Automatic Cell Synthesis Tool," Proceedings 26th Design Automation Conference, p.p., 239-244, June 1989.
  18. A. Domic, S. Levitin, N. Phillips, C. Thai, T. Shiple, D. Bhavsar and C. Bissell CLEO: A CMOS Layout Generator," Proceedings International Conference on Computer-Aided Design, p.p., 340-343, Nov. 1989.
  19. N. Weste, K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley Publishing Company, Reading MA, 1985.
  20. P. W. Kollaritsch and N. H. E. Weste, TOPOLIZER: An expert system translator of transistor connectivity to symbolic cell layout," IEEE Journal of Solid State Circuits, vol. SC-20, p.p., 799-804, June 1985.
  21. M. R. Garey and D. S. Johnson, Computer and Intractability: A Guide to the Theory of NP-Completeness, New York, W. H. Freeman, 1979.
  22. Gibbons A. Algorithmic Graph Theory, Cambridge, New York University Press, 1985.
  23. Bushnell Michael L., Design automation: automated full custom, Academic Press.
  24. R. Bar-Yehuda et al., Depth-first search and dynamic programming algorithms for efficient CMOS cell generation," IEEE Trans. Computer Aided Design, vol. CAD-8, pp 737-743, July 1989.
  25. M. L. Brady and M. Sarrafzadeh, Stretching a knock-knee layout for multilayer wiring," IEEE Trans Computer, vol. C-39, pp. 148-151, Jan 1990.
  26. Fang Jiaji, A new Fast Constraint Graph Generation Algorithm for VLSI Layout Compaction," IEEE International Symposium on Circuits and Systems v 5 1991, p.p. 2858-2861.
  27. de Lange A.A.J., Hierarchical Constraint Graph Generation and Compaction System for Symbolic Layout Generation, IEEE International Conference on Computer Design: VLSI in Computers and Processors 1989, p.p., 532-535.
  28. Kwon Yong-Joon, Fast Heuristics for Optimal CMOS Functional Cell Layout Generation," IEEE International Symposium on Circuits and Systems, Vol. 3 1988, p.p., 2423-2426.
  29. Mailhot and G. De Micheli, Automatic Layout and Optimization of Status CMOS Cells," Proc. Int. Conf. Comp. Des.-88 pp 795-801.
  30. B. W. Kernighan and S. Lin, An Efficient Heuristic Procedure for Partitioning Graphs," Bell Sys. Tech Journal, Vol 49, Feb 1970. pp 291-307
  31. D. D Hill Sc2D: A Broad-spectrum Automatic Layout System." Proc CICC-87 pp 729-732
  32. D. G. Baltus and Allen, SOLO: A Generator for Efficient Layouts from Optimizes MOS Circuit Schematics," 25DAC, 1988
  33. DD Hill et.al Algorithms and Techniqeust for VLSI Layout Synthesis. Kluwer Pubs 1989
  34. D. D. Hill Sc2: A Hybrid Automatic Layout System," Proc. ICCAD 1985, pp 172-174.