Due to the fixed layout and limited routing resources of
FPGAs, placement and routing is a very important issue in FPGAs.
In general, synthesis tools do not consider placement and
routing. Low-level operations such as place and route are
normally the problem domain of fitters, which understand the
architecture of the specific target device. Only so can one
expect reasonable operations, even though few fitters today
feature sophisticated place and route strategies.
Fitters also perform low-level optimizations to take full advantage of the target architecture. In many cases, these fitters are also responsible for mapping a generic net list onto LUT-based CLB structures. Depending on the synthesis tool used, partitioning into CLBs may occur either during the synthesis or routing step. A good example is Synopsys, which offers two different synthesis tools, Design Compiler and FPGA Compiler. While FPGA compiler understands the LUT-based structure of CLBs, Design Compiler views design as sea-of-gates structures, with each gate contributing a give delay.
Obviously, the FPGA compiler reports more accurate timing information and can perform better target-specific optimization. However, not all FPGA families are supported with FPGA Compiler. Thus, while the Xilinx 4k series is supported by FPGA Compiler (a library for Design Compiler also exists), the Xilinx 3k and 7k and the Altera Flex8000 [Alt93] families are only supported by Design Compiler. The level and quality of timing information given by Design Compiler varies, depending on the family. While Design Compiler does not provide any timing information at all for Xilinx 7k EPLD series [Xil94c], the Altera Flex8000 family does contain timing information.
The timing information provided by the Altera Flex8k library seems to contain worst-case timing information for single gates. Since multiple gates can normally be allocated to a single LUT, delays are grossly over-estimated. Realistic timing reports can only be generated after the placement and routing using Altera's fitter maxplus2 [Zha95].
As timing characteristics are influenced heavily by placement and routing in FPGA technology, meaningful gate-level simulation can only be performed with backannotated timing information generated by the appropriate fitter .