Computer Aids for VLSI Design

Steven M. Rubin

Copyright © 1994

Chapter 5: Static Analysis Tools

Section 6 of 6

5.6 Summary

This chapter has illustrated a number of techniques for the data-free examination of VLSI circuits. Such static analyses require a full topological description of the circuit that is often a product of node extraction. Geometric design rules check the layout of a circuit, and electrical rules check the topology. Verification tools check individual specifications to ensure that the design will perform as intended. The next chapter deals with actual performance considerations that can be analyzed by treating a circuit dynamically.

Questions

1. What is the problem with raster-based design-rule checking that does not occur with raster-based node extraction?
2. How can network-comparison methods fully describe the differences between dissimilar networks?
3. How would you program a preprocessor to convert design rules into state-based design-rule checking tables?
4. Why is timing verification more user-intensive than is design-rule checking?
5. Why is the functional verification of asynchronous circuits so difficult?
6. Why are rule-based systems an ideal choice for implementation of electrical-rule checkers?
7. What is the drawback of hierarchical design rule checking?

References

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• Shand, Mark A., "Hierarchical VLSI Artwork Analysis," VLSI '85, (Horbst, ed), 419-428, August 1985.
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• Trimberger, Stephen, "Automated Performance Optimization of Custom Integrated Circuits," VLSI '83 (Anceau and Aas, eds), North Holland, Amsterdam, 99-108, August 1983.
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• Wilmore, James A., "Efficient Boolean Operations on IC Masks," Proceedings 18th Design Automation Conference, 571-579, June 1981.

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