; Xilinx APR Constraints File ; These block names should match the labels attached to the pad ; components in the Viewdraw schematic ; Pads connected to bidirectional Buffer Module local bus place block DATA0PAD P72; place block DATA1PAD P53; place block DATA2PAD P56; place block DATA3PAD P58; place block DATA4PAD P59; place block DATA5PAD P60; place block DATA6PAD P61; place block DATA7PAD P62; place block DATA8PAD P63; place block DATA9PAD P65; place block DATA10PAD P66; place block DATA11PAD P67; place block DATA12PAD P68; place block DATA13PAD P69; place block DATA14PAD P70; place block DATA15PAD P71; ; Pads connected to active low SRAM control lines place block MEM_RWPAD P8; place block MEM_OEPAD P9; place block MEM_CEPAD P10; ; Pads connected to bidirectional SRAM data lines ; Note that arbitrary placement among these lines is possible ; which should simplify APR's routing job allow block MEM0PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM1PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM2PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM3PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM4PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM5PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM6PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM7PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM8PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM9PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM10PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM11PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM12PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM13PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM14PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; allow block MEM15PAD P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P2 P3 P4 P5 P6 P7; ; Pads connected to the SRAM address lines ; These may also be placed arbitrarily among the given set allow block ADDR0PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR1PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR2PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR3PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR4PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR5PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR6PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR7PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR8PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR9PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR10PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR11PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR12PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR13PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; allow block ADDR14PAD P11 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28; ; Input pads connected to signals provided by Bullwinkle GAL control logic place block EXTRACTPAD P35; place block TRIGGERPAD P40; place block CSPAD P46; ; Output pads connected to Bullwinkle control logic or to PC input port place block AFPAD P39; place block EMPTYPAD P45; place block FULLPAD P47; ; This pad is shared with the configuration signal Init ; and is sampled by the PC input port place block DEBUGPAD P42;