VHDL is a language that is used for two different purposes: simulation and synthesis. VHDL descriptions of a circuit can be behavioral or structural. To further complicate one's understanding of VHDL, different vendors have slight variations in syntax and library conventions that make writing VHDL that works with multiple software packages a real challenge.
Many designs that have nothing to do with logic synthesis are described using VHDL simply because of the importance of simulation. Microprocessors, memories, and even network and bus interfaces are examples of devices that are sometimes modeled using VHDL. In such models, it is very important to be able to include certain operational parameters such as propagation delay times, setup and hold requirements, and other timing characteristics.
If you are writing a VHDL module with the intention of using a logic synthesis program such as Synopsys on it, propagation delay times are obviously meaningless. Such characteristics depend heavily on the target device technology which VHDL is helping to abstract away from the design stage.
Synthesis software requires implementation hints that do not need to be present in VHDL for simulation. For example, numbers must be represented in some binary system (signed magnitude, two's complement, or otherwise) that must be determined by the designer and not the software. Because of this, while VHDL allows many different VARIABLE types and defines various operations on these types, for synthesis most values should be thought of as SIGNALs.
Behavioral descriptions of a circuit more closely resemble a high-level programming language and include constructs such as IF-THEN-ELSE-END IF, WAIT UNTIL, FOR loops, and possibly addition and subtraction operators. Very often a behavioral description will simulate fine and even synthesize without errors, but the logic inferred may be inefficient or even incorrect.
Structural VHDL involves the instantiation of COMPONENTs, such as logic gates, flip-flops, and higher level modules made up of simpler ones. The component PORT MAP statements basically "wire-up" the modules to each other or to inputs and outputs. If you find you must describe your circuit in this level of detail, you would probably find a schematic editor easier than writing VHDL code, especially for small projects.
On the surface the main differences are in the default data types recognized by the two environments, Viewlogic VHDL Analyzer and Synopsys Design Analyzer. Viewlogic signals by default are VLBIT and VLBIT_1D bit types ('0', '1', 'X', 'Z'), while Synopsys by default uses BIT and BIT_VECTORs ('0', '1'). For most synthesis projects you will need to use the STD_LOGIC and STD_LOGIC_VECTOR types provided by the IEEE library. At the top of each VHDL file include the statements:
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;Unfortunately, the Viewlogic VHDL Analyzer does not support the IEEE library. If you want to perform functional simulation using ViewSim, you must comment out the IEEE library statements and replace all STD_LOGIC types with VLBIT. If you need to switch back and forth between Synopsys and Viewlogic, you might consider using the C preprocessor and #define macros to switch easily between the two different VHDL formats (See Appendix C of the Address Tracing System). Another VHDL peculiarity to be aware of is what to call ports that are really outputs of a module but are also read by statements within that module. This happens very frequently, for example, in a shift register or any storage element with feedback. The VHDL compiler will complain if you call the port an OUT port and then read it, but it really isn't an INOUT port. The proper designation for such a port is a BUFFER. This works fine with Synopsys, but Viewlogic VHDL Analyzer won't recognize the BUFFER keyword, so you must call the port an INOUT.