Summary of commands and their effects
Where did that .rbt file come from? What file does PPR use as
input? Hopefully searching for such keywords on this page will answer
some of these mysteries.
- source /opt/digital/setup_synopsys
- Adds the appropriate Synopsys paths and shell variables to your
current environment. Use setenv CAD_SILENT first if you don't
want it to print anything.
- source /opt/digital/setup_other_cad
- Adds the appropriate Xilinx paths and shell variables to your
current environment. This currently sets up the XACT 5.1 path
/opt/digital/share/xilinx3.
set path=($path /opt/digital/share/xilinx3/xact/bin/sparc \
/opt/digital/share/xilinx3/workview/bin/sparc)
setenv XACT /opt/digital/share/xilinx3/xact:/opt/digital/share/xilinx3/workview
- dc_shell
- Synopsys Design Analyzer Command Shell. This is the
non-graphical version of the Synopsys Design Analyzer. It is useful for
running script files (.dcsh) from the command line or from a
Makefile. Stores designs in .db format but can export to a
variety of file types including EDIF (.sedif) and a Xilinx
netlist format (.sxnf) for xmake.
- design_analyzer
- Synopsys Design Analyzer. Graphical tool which allows access to VHDL
compiler (Design Compiler), mapping and optimization tools for Xilinx (FPGA
Compiler for XC4000), and speed and area information. Automatically
generates a hierarchical or flattened schematic of the mapped design. All
menu options are equivalent to a shell command that can be seen by viewing
the command.log and used in your own dc_shell scripts.
- iview
- Worldview: Synopsys Online Documentation. Run
/opt/digital/synopsys3.2b/worldview/bin/iview if the
correct iview is not in your path.
- powerview (Powerview Cockpit)
- Typing powerview launches the Powerview Cockpit,
assuming you have alias powerview 'cd ~/powerview;
/opt/digital/bin/powerview' in your .cshrc file.
From this you can launch Viewdraw, Viewsim, ViewPLD, VHDL
Analyzer, etc. You can also run Xilinx XDM
from the Cockpit if you have the All Programmable Design tool
drawer selected.
- Powerview->Project->Create
- You enter a full directory path for a project to create. If the
directory does not exist, Powerview creates it. It then creates
three subdirectories, wir, sch, and
sym for the project's wirelist, schematic, and symbol
files. It also copies your ~/powerview/standard/viewdraw.ini file to the directory
which you can then modify to specify project-specific library paths.
- viewsim
- Viewlogic ViewSim logical simulator: input netlist is in .vsm
format; for simulation of VHDL files also requires a .vli file for each
module. Can execute command scripts (.cmd) and optionally produces .log
files and .wfm files.
- viewdraw
- Viewlogic ViewDraw schematic editor: edits schematic and symbol
files in sch and sym directories (design.1, etc.). Can write
wirelist in wir directory. Provides easy access to xc3000/xc4000
macro components and building blocks if viewdraw.ini file is set up
correctly.
- vhdl
- Runs Viewlogic VHDL Analyzer from the command line (also
available from Powerview's default drawer). Produces .vli and
.vsm (with -V option) files for ViewSim from .vhd source. These
allow logic-level simulation (without accurate gate delays).
This is good for gaining familiarity with small VHDL modules but
for FPGA designs you should use Synopsys followed by XSIMMAKE for accurate timing.
- vsm
- Viewlogic VSM Netlister: takes wirelist from wir directory and
produces simulation netlist (.vsm) for ViewSim.
- make
- Make: helps to maintain up-to-date versions of programs or
projects. Input is a Makefile which specifies the file
dependencies and translation rules. Provides a good way to
automate sequences of command-line utilities, but a lot of the
Xilinx utilities you used to have to run yourself are now
automated very smoothly by xmake and xsimmake.
- RCS
- Revision Control System: includes the programs co (checkout), ci
(checkin), rcs, rcsdiff, rlog. For large or multi-person
projects you should learn how to use RCS and manage your VHDL
source files. Type man rcsintro.
- XDM
- Xilinx Design Manager: provides easy access to a variety of
programs and allows you to choose among cryptic command-line
options with a mouse. Programs include XDE/Editlca for viewing the placed and routed
FPGA internals, XMAKE for automating
translation of Synopsys output or wirelists into FPGA programming
files, and XSIMMAKE for extracting the
timing information from XMAKE's output for simulation.
- XDM->XDE->EditLCA
- A graphical tool which allows you to examine the layout of the
FPGA. The array of CLBs is shown surrounded by the IOBs and pads,
connected by the programmable switch networks. To view the
functions and flip-flop connections inside a CLB or IOB, select
Blk->EditBlk and click on the block. To return to the layout,
select Blk->EndBlk.
- xmake
- Xilinx XMAKE utility: Automatically executes the proper sequence
of Xilinx command-line tools for translation of FPGA designs
depending on the part type. For XC3000 FPGAs, it runs
syn2xnf, xnfmerge,
xnfprep, xnfmap,
map2lca, apr, and makebits. For XC4000 FPGAs, it runs ppr instead of apr, and for Viewlogic designs it
runs wir2xnf instead of syn2xnf. These
tools and their options tend to vary from version to version, so
XMAKE hides many of these details from the user.
- xsimmake
- Xilinx XSIMMAKE utility: Performs one of several simulation
preparation flows. The Viewlogic_Fpga_Func flow duplicates a
Viewlogic schematic hierarchy and produces a functional
.vsm simulation file only. The Viewlogic_Fpga_Timing flow uses
the output of the XMAKE process (.lca file) and produces a .vsm
file with post-routing delays for simulation with ViewSim. It
runs xdelay, lca2xnf, xnfba, xnf2wir, then vsm.
- syn2xnf
- Part of Xilinx/Synopsys Interface package: converts a Synopsys
.sxnf or .sedif file to Xilinx .xnf format.
- wir2xnf
- Converts Viewlogic wirelists (e.g. wir/design.1) into Xilinx
.xnf format for each component in the design hierarchy.
- xnfmerge
- Combines all the .xnf files for a design hierarchy into one
flattened .xff file.
- xnfprep
- Takes a flattened XNF file (.xff), checks for design rule
violations and warnings such as very high fanout, gated clocks,
and combinational feedthroughs, trims unnecessary logic and
writes an .xtf file, and produces a human-readable .prp summary
file.
- xnfmap
- Translates an .xtf file into a .map file, mapping logic to the
actual FPGA logic blocks.
- apr
- Automatic Place and Route program for XC3000 parts. Uses a .map
file as input and an optional .cst constraint file to specify pad
locations. Produces an .lca file that can be viewed with
XDM->XDE->Editlca.
- ppr
- Partition, Place, and Route program for XC4000 parts. Uses a
.map file and an optional .cst constraint file, produces an .lca
file.
- makebits
- Produces .bit file for downloading to an FPGA from .lca file.
Optionally produces a .rbt rawbits file which has one bit per character
and hence is bigger but simpler to read.
- xdelay
- Traces paths in the LCA layout and writes timing information into
the .lca file.
- lca2xnf
- Translates an input .lca design file into an .xnf file with delays.
- xnfba
- Back-Annotates the output of lca2xnf with labels from the .xff
file, since the apr/ppr process cause some names to be lost.
Produces a single xnfba.xnf file.
- xnf2wir
- Converts an .xnf file into a Viewlogic wirelist for use by vsm
and ViewSim.
Created by Scott E. Harrington, Duke Electrical Engineering