The subject matter of using CAD software is presented most effectively using an on-line hypertext tutorial. As you browse, be sure to take advantage of the ability to jump to related documents as you have questions. You should especially make use of cut-and-paste to copy commands and sample code into your own shells, scripts, and programs.
FPGA (field programmable gate array) devices allow rapid design prototyping. They offer more dense logic and less tedious wiring work than discrete chip designs and faster turnaround than sea-of-gates, standard cell, or full-custom design fabrication. FPGA designs can be created in a number of ways, including graphical schematic component layout (Powerview) and hardware description languages such as ABEL, VHDL, and Verilog.
VHDL (VHSIC hardware description language) can be used either for behavioral modeling of circuit designs or for logic synthesis using either behavioral or structural descriptions. Since writing structural circuit descriptions is like trying to describe a circuit using text instead of a schematic editor, the real advantage of VHDL is seen only in its behavioral synthesis potential. At Duke, VHDL synthesis can be performed by either Synopsys tools or by Mentor Graphics' Autologic tool.
This tutorial is for VHDL synthesis using Synopsys, simulation using Viewlogic Viewsim, and Xilinx X3000 and X4000 FPGA devices.