To help put VHDL into a proper context and emphasize its use as a design entry language, this chapter presents several sample circuits and shows how they can be described for synthesis and testing.
In addition to the quick introduction to VHDL presented in this chapter, there are some very important concepts that will be introduced. Perhaps the most important concepts to understand in VHDL are those of concurrency and hierarchy. Since these concepts are so important (and may be new to you), we will introduce both concurrency and hierarchy in these initial examples. First, though, we will present a very simple example so you can see what constitutes the minimum VHDL source file.
As you look at these examples and read the information in this chapter, you will begin to understand some of the most important concepts of VHDL, and you will have a better understanding of how the more detailed features (covered later) can be used.
This comparator accepts two 8-bit inputs, compares them, and produces a 1-bit result (either 1, indicating a match, or 0, indicating a difference between the two input values).
A comparator such as this is a combinational function constructed in circuitry from an arrangement of exclusive-OR gates or from some other lower-level structure, depending on the capabilities of the target technology. When described in VHDL, however, a comparator can be a simple language statement that makes use of VHDL's built-in relational operators.
-- Eight-bit comparator -- entity compare is port( A, B: in bit_vector(0 to 7); EQ: out bit); end compare;
architecture compare1 of compare is begin EQ <= `1' when (A = B) else `0'; end compare1;Note: In this and other VHDL source files listed in this book, VHDL keywords are highlighted in bold face type. In some VHDL books and software documents, keywords are highlighted by using upper case characters for keywords and lower case characters for identifiers. Some other books and manuals use lower case for keywords and upper case for identifiers.
Whatever forms you encounter or choose to use, keep in mind that VHDL itself is case-insensitive: keywords can be entered using either upper or lower case, and identifiers (such as signal and variable names) may be entered in either case as well, with no distinction being made between identifiers that are written in either case.
One more note: In the above context, the VHDL symbol <= is an assignment operator that assigns the value on its right to the signal on its left. Any text that follows "--" is a comment and is used for documentation only.
Now let's look more closely at this source file. Reading from the top, we see the following elements:
An entity declaration describes the circuit as it appears from the "outside" - from the perspective of its input and output interfaces. If you are familiar with schematics, you might think of the entity declaration as being analogous to a block symbol on a schematic.
The second part of a minimal VHDL design description is the architecture declaration. Before simulation or synthesis can proceed, every referenced entity in a VHDL design description must be bound with a corresponding architecture. The architecture describes the actual function?or contents?of the entity to which it is bound. Using the schematic as a metaphor, you can think of the architecture as being roughly analogous to a lower-level schematic referenced by the higher-level functional block symbol.
Let's take a closer look at the entity declaration for this simple design description:
entity compare is port( A, B: in bit_vector(0 to 7); EQ: out bit); end compare;The entity declaration includes a name, compare, and a port statement defining all the inputs and outputs of the entity. The port list includes definitions of three ports: A, B, and EQ. Each of these three ports is given a direction (either in, out or inout), and a type (in this case either bit_vector(0 to 7), which specifies an 8-bit array, or bit, which represents a single-bit value).
There are many different data types available in VHDL. We will cover these types later in this chapter, and in greater detail in Chapter 3, Exploring Objects and Data Types. To simplify things in this introductory circuit, we're going to stick with the simplest data types in VHDL, which are bit and bit_vector.
Here's the architecture declaration for the comparator circuit:
architecture compare1 of compare is begin EQ <= `1' when (A = B) else `0'; end compare1;The architecture declaration begins with a unique name, compare1, followed by the name of the entity to which the architecture is bound, in this case compare. Within the architecture declaration (between the begin and end keywords) is found the actual functional description of our comparator. There are many ways to describe combinational logic functions in VHDL; the method used in this simple design description is a type of concurrent statement known as a conditional assignment. This assignment specifies that the value of the output (EQ) will be assigned a value of `1' when A and B are equal, and a value of `0' when they differ.
This single concurrent assignment demonstrates
the simplest form of a VHDL architecture. As you will see, there are many
different types of concurrent statements available in VHDL, allowing you
to describe very complex architectures. Hierarchy and subprogram features
of the language allow you to include lower-level components, subroutines
and functions in your architectures, and a powerful statement known as
a process allows you to describe complex registered sequential logic
as well.
And that's just the beginning of the
beginning. This "First Look" chapter of VHDL Made Easy! goes on
to discuss data types, design units, entities, packages, package bodies,
configurations, levels of abstraction, conditional and selected signal
assignments, and a whole lot more. Plus, there are lots of examples to
guide you. Order your copy and find out how easy it is to enhance your
career skills with VHDL!