Procedural Modeling #2

Control Flow Sequential Statements

Sequential statements tend to look a lot like most modern structured programming languages, and can be used in much the same way.

Conditional Control

if condition1 then
sequential statements
elsif condition2 then
sequential statements
.
.
.
else
sequential statements
end if;

Example:
 

 if  memreq  = '1' then
        if  read = '1' then
                memdata <=  MEM ( address );
        else
                MEM (address) <=  memdata;
        end if;
end if;
 
(We assume here that memreq and read are type BIT, not BOOLEAN.)

 

Selected Control

case selector is
when value =>
sequential statements
when value |value =>
sequential statements
when discrete_range =>
sequential statements
when OTHERS =>
sequential statements
end case ;
 
Example:  (low level, timing, often not synthesizable or produces very simple elements)
 
case X_in is
        when '0' =>
                y_out <= '1' after tph;
        when '1' =>
                y_out <= '0' after tpl;
        when 'X' =>
                y_out <= 'X' after (tph+tpl)/2;
                        y_out <= 'X' after tpl;
end case;

In this example we are modeling an inverter.  The draft synthesis standard states that synthesis tools should ignore 'X' and 'U' branches of selected signal assignment statements.  The synthesis tool will begin by producing a multiplexor with '1' connected to the I0 input and '0' connected to the I1 input.  it will then optimize by eliminating inputs to AND gates tied to '1' and eliminating AND gates with a '0' input by connecting the output signal  to '0'.  '0' inputs to OR gates are eliminated, and '1' inputs to an OR gate allows elimination of the OR gate.  You can easily see that these rules simplify the multiplexor above to a simple inverter.

Example:  Multiplexer
 

case Current_state is
        when sv0 => next_state <= sv1
        when sv1 => next_state <= sv2;
        when sv2 => next_state <= sv3;
        when sv3 => next_state <= sv0;
end case;
 
Example:  Multiplexer or combinational logic
 
case Current_state is
        when sv0 | sv1 | sv2 => Z_out <= '0';
        when sv3 => Z_out <= '1';
end case;
 
These two examples are part of processes used to model finite state machines.  They do not include the clocked behavior, and model only the combinational logic part of the design.

While Loops

while condition loop
sequential statements
end loop;

Example:  (not synthesizable)

 while chang_req = '1' loop
        wait until ad_valid_a = '1';
        bus_data <= data_src;
        msyn <= '1' after 50 ns;
        wait until ssyn = '1';
        msyn <= '0';
end loop;

In general, while loops have time-varying conditions which do not lend themselves well to synthesis.

For Loops

for index in range loop
sequential statements end loop;

Example: where x_in is an array of inputs
 
tval(left) := x_in(left)
for i := x_in'left'succ to x_in'right loop
        new_val := new_val and x_in(i) ;
end loop;

Synthesizable FOR loops produce a result similar to concurrent VHDL FOR GENERATE statements.

The synthesis tool will generate a cascade of two input AND gates from the description above.  Timing optimization will attempt to compress the circuit into a minimum number of levels, balancing the tree of AND gates and using the largest input AND gates available in the library and useful in the optimization.

Branching within a loop - Not generally synthesizable

Next branches back to the beginning of the loop (like a Fortran CONTINUE statement).
loop
sequential statements
next when condition
sequential statements
end loop;
Exit branches completely out of the loop to the first statement following the end loop;
loop
sequential statements
exit when condition
sequential statements
end loop;
Example: where x_in is an array of inputs

 

for i := 2 to x_in'length loop
        new_val := new_val and x_in(i) ;
        exit when  new_val = '0';

end loop;

Process Termination

wait;
With no condition to ever be satisfied, the process will never resume.

Sequential Assertion Statements

assert valid_condition ;
report error_message
severity level;
where the level may be NOTE, WARNING, ERROR or FAILURE
 
Synthesis tools do not generate anything from assertion statements

Assertions provide information about how the design unit is to be used. This is an aspect of the design interface which has traditionally been relegated to comments. In VHDL an assertion can be used as an executing "monitor" during simulation.

Assertion Examples
 

assert  not ( preset = '0' and clear = '0' )
        report "Preset and Clear both active on JKFF"
        severity Note;

assert  not clock'event or
        (J'Stable(setup) and K'Stable(setup) )
        report  "J or K input changed during setup"
        severity Warning;

assert not data_valid'event or Data_bus'Stable ( setup )
        report "Data on System bus not stabilized at use"
        severity Warning;

It is also possible to create procedures which check behavior. This permits encapsulation of entire checking "bodies."  This is perhaps where sequential assertion statements become most useful.  By invoking a concurrent procedure, it is possible to run through a sequence of condition checks without making the simulation tool manage event queues and call many mini-processes to perform the same evaluation.

Check_setup_hold (clk, J, K, Tsetup, Thold);

Rev. 2/19/98 B. Huey