CSE 518 Lecture #1

Introduction

Syllabus

Prerequisites
Textbook
Course accounts and ERC 208
Laboratory assignments and use of Mentor Graphics Tools

Introduction

Background: HDL's since the 1960's, VHSIC initiative, IEEE 1076, IEEE 1164, related standards, acceptance and use.

Applications of Hardware Description Languages

specification
documentation
verification
test
synthesis

Motivations for creating / using VHDL

standardization of documentation
decreased system design time and cost
open-system CAE tools
improved integration of multi-vendor designs
improved understanding of design science

Background

1960's - 1980's
AHPL, CDL, DDL in classroom. Number of languages mushrooms to over 200 languages, all of them either proprietary or academic

1983 VHSIC Program initiates definition of VHDL

1987 VHDL Standard (IEEE 1076) approved

1990 Verilog dominates the marketplace.
VHDL gaining acceptance as the second language due to standards effort and DoD mandated use.

1992 IEEE 1164 (3, 4, 9-valued logic standard adopted)

1993 VHDL re-balloted
minor changes make it more user-friendly.

1994 Widespread acceptance of VHDL.
CAE tools operate at speeds comparable to Verilog. Mentor, Cadence, Viewlogic, Synopsys all provide full VHDL compilation / simulation and synthesize with subsets of VHDL.

Modeling and Design Space

Axes and Levels of Representation

VHDL does not support physical dimension very well -- but that is what synthesis must map the design to. Vendor supplied and user-specified attributes help to make VHDL adequate for mapping to the physical dimension of design.

Information shown on each axis of representation

VHDL:

is very good for behavioral description
involves verbose structural descriptions,
provides outstanding configuration management for structures,
does not support physical dimension very well -- but that is what synthesis must map the design to.

It is extremely important to ensure that

the hierarchical form is consistent from axis to axis
information is consistent across the entire design (across all viewpoints of the design)

Domains of activity for design tools

Note that simulation occurs on the behavioral axis. Even structural models (e.g. netlists) have to be interpreted behaviorally by event protocols on the nets themselves, and by procedural models of the elements (e.g. gates and flipflops) being simulated.

The synthesis process requires

Translation between axes. Substitution of an equivalent structural architecture for a behavioral module.
Example: Replacing a procedural description of the operations to be performed by an ALU with the structure for the ALU.
Translation down an axis. Substitution of a more detailed description for the higher level abstraction
Example: substituting the gate level description for the MSI symbol of a multiplexor)
Example: replacing integer range 0 to 255 with std_logic_vector ( 7 downto 0)
It is critically important that as the design proceeds to increasing detail and from behavioral axis => structural axis => physical design that changes to the specification be reflected back into the more abstract models of the initial design.
This is especially important in adding detail to the design: e.g. synchronization and timing, back annotation as drive capabilities and path delays are determined.

Alternative paths to realization exist:

full custom design: structure to flexible cells
standard cells: substitute structural models for equivalent cell layouts
gate arrays: map gate models into FPGAs
PLA's: map directly from behavioral equations and finite state machines to PLAs

Applications of Hardware Description Languages

It is important to understand that hardware description languages (HDLs) exist to satisfy a variety of purposes and are used in a number of different ways. Therefore, there are features of VHDL (and any other design language) that will be useless in some applications, and confusing in other applications. Some descriptive features of VHDL may even lead to bad synthesis. A major aspect of this course will be understanding how VHDL should be used to permit synthesis tools to produce good implementations of designs.

To understand why VHDL looks the way it does, it will help to examine the variety of purposes it serves.

Design Specification
Design Documentation
Design Verification
Product Test Generation

HARDWARE SYNTHESIS

Design Specification

Definition of functional interfaces

concurrent ==> structure (space)
sequential ==> behavior (time)

Definition of functions of the design (behavior)

by control flow (procedural)
by data flow (concurrent)

Project partitioning

in space (structural)
in time (behavioral)

Design Documentation

Language standardization: to improve quality and efficiency of communication, broaden audience
Interface description for users: often as components of next level higher system: physical, structural, and "pin" functions
Express usage constraints: e.g. disallowed input timings, combinations, output loads
Express functional behavior of the design:: internal states, data structures (e.g. format used in a floating point unit) algorithms implemented
Show communication protocols between design entities

Design Verification

SIMULATION -- The Usual Method highly developed tools inherently behavioral (structural simulators consist of ordered calls to primitive procedures to model corresponding primitive structures) limited by the effectiveness of the design test program developed
Formal verification methods require common language for: specification of design goals and description of implementation to meet those goals formal (mathematically rigorous) language definition to permit logical transformation of descriptions to prove equivalence. Such mathematical languages inherently are declarative language that can describe both time and structure
Correctness by construction (silicon compilation) is more nearly realized than automatic verification systems

Product Test Generation

This is Dr. Huey's primary area of research, and a major topic of CSE 516.

Hardware Synthesis

stepwise refinement of design by architectural decomposition (either structural or behavioral)
transformations from behavioral models to corresponding structural and physical models
e.g. PLA generators, standard cells for shift registers, adders, etc.
relating scaling parameters with expressions
enforcement of design constraints
register transfer level allocation, dataflow optimizations<
expression transformations for optimization

VHSIC Motivations for Creating / Using VHDL

Standardization of Documentation: improved communication of requirements between military, contractors, and subcontractors
System Design Time and Cost reduced ambiguity in specification of design interfaces and design functions reusability of existing designs
Open-system CAE Tools: can change CAE system without losing use of existing designs elimination of language translators
Improved Integration of Multi-vendor Designs: shared design databases become possible -- standard cells, behavioral models
Improved Understanding of Design Science: top-down, middle-out, bottom-up

Copyright 1997, Ben M. Huey
Copying this document without the permission of the author is prohibited and a violation of international copyright laws.

Rev. 1/28/98 B. Huey