The growth of graphics oriented operating systems and applications has created a data bottleneck between the processor and peripherals. To address this problem, the Peripheral Component Interconnect (PCI) local bus was developed to handle graphics and other high bandwidth needs (such as disk and LAN I/O) of high performance computers. The PCI local bus is implemented as a high performance 32-bit or 64-bit bus with multiplexed address and data lines. As an open standard, the PCI local bus is now common in many PCs and workstations. Some estimates indicate that 40% of new PCs, workstations, and portables will use the PCI local bus in 1996. The PCI local bus specification was originally issued in June 1992 and recently updated in June 1995 as revision 2.1.
Advances in semiconductor complexity, density, and packaging have created a challenge to manufacturing and test due to increased pin counts, reduced pin spacing, and inaccessible circuit nets. Interconnect faults, such as opens and shorts, typically account for 75% or more of the manufacturing defects (see Optimizing Fault Detection for Boundary Scan Testing). There are many causes of opens and shorts; including bent pins, too much solder, too little solder, component alignment, and others, but most are detected by an interconnect opens and shorts test. To address the problem, a structured interconnect test and access method was needed. This need was addressed by the Joint Test Action Group (JTAG) and was formalized in 1990 as the IEEE Std. 1149.1-1990, Standard Test Access Port and Boundary Scan Architecture. IEEE 1149.1 consists of a 4-wire (optionally 5-wire) serial test bus with a standard protocol and a structured test technique called boundary scan. Boundary scan logic placed at the I/O pins of a component allows each pin to be controlled or observed for interconnect test.
The PCI local bus developers recognized the importance of test and reserved five signal pins for the IEEE 1149.1 test bus. The PCI local bus specification allows the IEEE 1149.1 to be connected in a system in three ways: 1) the reserved motherboard signals are no-connects, 2) each PCI slot has its own IEEE 1149.1 ring, 3) utilize a IEEE 1149.1 multi-drop addressable connection IC on the add-in cards. The first option does not provide any in-system test access so IEEE 1149.1 capabilities are "lost" at the system level. The second option can be used with a IEEE 1149.1 scan path partitioning IC, such as a SN74ACT8997 Scan Path Linker, added on the motherboard. The third option can be used by adding a multi-drop addressable IEEE 1149.1 connection IC, such as a SN74ABT8996 Addressable Scan Port, on the PCI add-in cards.
The current version of the PCI specification, revision 2.1, does not require a specific method to implement IEEE 1149.1 at the card or system level. While this allows flexibility, it also allows non-interoperable situations. Obviously a complete system solution should implement a common test access method for both motherboard and add-in cards. The method discussed here is, like the PCI local bus, a multi-drop solution. Designers should note that IEEE 1149.1 requires IC internal pull-up resistors on TMS and TDI signals so they should not be tied directly to VCC or GND on add-in cards or motherboards. Also, exercise care when routing the TCK and TMS signals to minimize noise or signal reflections. The PCI specification states that add-in cards which do not implement IEEE 1149.1 should have TDI tied to TDO. This is not recommended because it prevents the multi-drop solution from working.
Since it's development, IEEE 1149.1 was quickly adopted by complex and critical products such as telecommunications, high-end computers, avionics, and office products. It's usage in cost-sensitive consumer markets such as PCs has begun to increase as the products' complexity and density increases, starting with server-class products.
The early adopters of IEEE 1149.1 implemented it for its original purpose, manufacturing defects testing. However, many companies are now realizing that IEEE 1149.1 can provide a gateway to other value added capabilities such as, design debug and validation, internal IC test, on-chip emulation, performance monitor logic, and system test features. For example, the TMS320 family of Digital Signal Processors has been one of the first IC families to use the IEEE 1149.1 test bus to access and control on-chip performance monitor and on-chip emulation logic as part of TI's Digital Signal Processing Solutions (DSPS) strategy. IEEE 1149.1 can be used throughout the life of the product for hardware and software integration, troubleshooting, and upgrades.
The ring architecture of IEEE 1149.1, which provides a simple interconnect and low gate count implementation of single board/card designs, presents a potential problem for multi-card system architectures. Many systems provide add-in card expandability using multiple card slots. An open slot results in an open ring thus preventing IEEE 1149.1 communications. Although a star architecture is supported, it requires individual TMS signals per slot. A less costly system approach would support a flexible multi-drop bus in a multi-add-in card system architecture.
To provide a flexible multi-drop bus system solution, while still allowing native IEEE 1149.1 protocol, TI developed the Addressable Scan Port (ASP). The ASP operates using a shadow protocol which is compatible, yet transparent, with the IEEE 1149.1 protocol. The result is a low-cost, small footprint (24-pin TSSOP) IC with the ability to selectively connect to individual add-in cards for control and testing via IEEE 1149.1. Conceptually the ASP can be thought of as an IEEE 1149.1 switch, which, via shadow protocol, closes or opens to make or break the IEEE 1149.1 ring. To simplify manufacturing test, an ASP connection can be forced by simply setting the BYPASS pin active. No additional bits are added in the scan chain. Tests are treated in an object oriented manner because card tests are reusable, without modification, in the system. Up to 1021 ASPs can reside on a multi-drop bus to be selectively addressed for individual tests or globally controlled for BIST operations.
To demonstrate and validate the use of IEEE 1149.1 in a common multi-drop multi-card system, a PC with an integrated PCI local bus was selected as a proof-of-concept system. The PC system consists of an off-the-shelf Pentium-based PC motherboard with three PCI bus slots and three PCI add-in cards (see Figure 1). As previously mentioned, the motherboard PCI bus has 5 pins reserved for IEEE 1149.1 signals. The IEEE 1149.1 pins, initially no connects on this motherboard, were connected in a multi-drop (bused) fashion.
Three PCI add-in cards, each containing one or more IEEE 1149.1 ICs, were used in the proof-of-concept system. The first PCI card is a TI ThunderLAN(TM) network interface card. The ThunderLAN card supports 10BaseT, 100BaseT, and 100VG-AnyLAN operation. The second PCI card is a TI TMS320C50-based DSP audio card. The third card is a PCI boundary scan demonstration card containing SN74BCT8244 8-bit octal buffers and SN74ACT8994 Digital Bus Monitor (DBM) ICs which act as a PCI bus monitor. All three PCI add-in cards were modified to include a TI SN74ABT8996 Addressable Scan Port (ASP) IC to connect the backplane IEEE 1149.1 bus to the card's internal IEEE 1149.1 bus.
Figure 1. PCI local bus/IEEE 1149.1 Proof-of-Concept System
The combination of a multi-drop PCI local bus, IEEE 1149.1 signals on the backplane, and PCI add-in cards with ASPs demonstrates a flexible, hierarchical embedded test solution . With a multi-drop IEEE 1149.1 bus implementation, the insertion or absence of PCI add-in cards no longer presents a problem of an open IEEE 1149.1 scan ring. A complete system solution would also include the Pentium processor and it's chipset in the IEEE 1149.1 scan chain. This can be accomplished by adding an ASP on the motherboard to selectively test it also.
The proof-of-concept system demonstrates several capabilities. For example, system test configuration information is determined by polling the system to resolve which PCI add-in cards are installed. In addition to determining the card addresses, each ASP address is encoded in this system to also convey the PCI add-in card type. The process is straightforward. First, the target PCI add-in card is addressed by transmitting the ASP selection protocol, which then connects the addressed add-in card to form a IEEE 1149.1 scan ring. After determining the type of PCI add-in cards present, card specific test vectors are applied for test or diagnostics. Due to the transparent nature of the ASP, IEEE 1149.1 test vectors for the add-in cards are reused without modifications so that scan-based tests, as well as diagnostics, are applied in-situ. Even more uses are possible, such as, in-system on-chip emulation control and performance monitoring using the IEEE 1149.1 test bus as a non-intrusive access path.
Even though this proof-of-concept platform only utilizes three PCI add-in card slots, much larger systems (or buses) are accommodated because of the large address space of an ASP. The advantages of incorporating a standard multi-drop test access method spans the whole range of product levels from, add-in card manufacturers, PC manufacturers, PC integrators, and even consumers. Without a common multi-drop access method, much of the advantages of test pattern reusability, portability, and development is lost.
This article described a multi-drop IEEE 1149.1 system architecture used with the PCI local bus. Considering the wide variety of PCI local bus add-in cards, the system test architecture must be thoughtfully selected. The proof-of-concept system demonstrated the feasibility and features of a multi-drop IEEE 1149.1 architecture. The PCI standards working group can improve IEEE 1149.1 interoperability by further defining the IEEE 1149.1 interconnect architectures supported. A preferred approach should be clearly described and encouraged.
The integration of IEEE 1149.1 with the PCI local bus provides a flexible solution serving engineer's needs for design verification, integration and manufacturing test while also meeting the consumer's needs of PCI local bus high speed and interoperability as well as in-system diagnosability. The multi-drop solution discussed here using addressable connection devices supports this and other larger systems needs for test and diagnostics reuse during manufacturing, integration and field levels.
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