This article presents a number of testing problems and shows how boundary-scan testing and TI products can be used to solve them.
The current approach to detecting board-etch and solder-joint faults in today's electronics industry uses two forms of Automatic Test Equipment (ATE): bare-board testers and digital in-circuit testers. Bare-board test is done after board fabrication. Tests for open-etch circuits between nodes force a voltage onto one circuit node and sense the voltage at another circuit node. This technique is used only on a raw, unassembled board.
An in-circuit test is done after board assembly and checks for:
Software models of each part on a board are used to generate the test patterns used by the in-circuit tester. The main assumption is that both board and in-circuit testers require physical access to nodes or points on the board in order to perform the necessary testing. Both testers require the ability to inject a voltage or current onto a nodal network and sense the voltage or current at another point on the network.
Higher-density packaging technologies, finer-pitch board etch, and more complex digital integrated circuits have made bare-board and in-circuit testing much more expensive.
Several testability products from Texas Instruments lend themselves to support IC-to-IC continuity testing. The techniques outlined allow detection and in most cases, isolation of board-etch and solder-joint faults, without forcing any additional requirements on the electrical design engineer. ASIC devices with boundary-scan cells (BSC) and bus interface components allow controlled insertion of digital logic values onto a nodal network by a driver-integrated circuit. This provides the means to sample the digital logic values on all receiver integrated circuits connected to a particular network. Broken-etch and solder-joint faults can be detected and isolated in this manner.
In the simple circuit shown in Figure 7-1, one driver (IC #1)
on a network drives digital logic values while the other receivers
(ICs #2 and 3) sense changing values on the net. If multiple driver
lCs exist on a network, each driver is allowed to drive in turn
while all receivers sense to detect and isolate a fault to a specific
driver or portion of the net.
Figure 7-1. Etch/Interconnect Testing
If an etch is broken on a network or an IC is not soldered to
the board properly, then nodes of some ICs are not connected to
nodes on others as shown in Figure 7-2 and Figure 7-3. When driver
IC #1 drives, only IC #2 senses the correct logic value, IC #3
does not.
Figure 7-2. Open-Etch Condition
Figure 7-3. Open-Solder-Joint Condition
If an etch is shorted to ground or power due to a solder fault,
then none of the ICs are able to drive or sense the correct logic
values. See Figure 7-4.
Figure 7-4. Short-to-Ground Condition
The overall coverage of etch- and solder-fault detection and isolation depends on the percentage of a board's circuitry that has boundary-scan architecture. Only networks driven by BSCs or IEEE 1149.1-compliant ICs can be tested in this way; nonscan-controlled networks require conventional approaches.
Because the driver and receiver BSCs are in silicon within the
ASIC, this technique can be used to test silicon bonding to package
pins in the integrated circuit foundry. A simple bond-out tester
can drive a logic value to an input pin of a IC and the sensing
function can occur on the BSC buffering the input to the core
logic of the ASIC. The reverse procedure can be used on an output
pin of an IC, the BSC driving the output of the core logic forces
a logic value that the bond-out tester senses and records. See
Figure 7-5.
The current technique used to detect and isolate board-etch and solder-joint faults remains unaltered. With TI's suite of testability products, board testing can be performed without external digital in-circuit testers. Boundary-scan architecture eliminates the need for physical probe points on printed-circuit boards that contain advanced-packaged, surface-mount integrated circuits. The need to develop part models for in-circuit test generation is also eliminated.
Complex digital designs use large-scale integrated circuits and ASICs to accomplish many functions on compact circuit boards. Not all logic functions are integrated, so discrete devices are still used for some functions. Discrete logic seldom includes boundary-scan test architecture due to the expense and complexity; these parts must be tested another way.
Testing discrete logic functions on a board has to be done from the boundary of the logic cluster. Combinatorial logic is normally driven by and into sequential elements such as a register or a clocked ASIC. By replacing the register with a IEEE 1149.1-compliant device, or by using Texas Instruments IEEE 1149.1-compliant macro cells at the boundary of the ASIC, the cluster logic may be easily tested. By using members of TI's family of testability products, a higher percentage of circuitry may be tested while reducing the vector count necessary to perform a functional test.
Figure 7-6 shows a simple circuit incorporating combinational
logic sandwiched between sequential logic.
During normal circuit operation, the IEEE 1149.1-compliant device drives the glue logic through to the BSCs in the ASIC. Two methods may be used to perform a test of the logic cluster using the TI family of testability products. There are benefits and drawbacks to both methods.
Deterministic test vectors scanned into the UUT can pinpoint a problem more easily than signature analysis. Since the exact input stimulus is known, the failing response can be detected. Deterministic test vectors perform a complete and meaningful test, but consume a lot of time and enough memory to store all vector data for both stimulus and response.
Signature analysis can be performed quickly and virtually automatically. After valid pattern generation and signature analysis seed values are obtained, the resultant signature can be checked against the correct value. This test can be performed at the scan clock speed and requires very little memory for data storage. However, the fault cannot be located without using an extensive fault dictionary.
Signature analysis requires that the IEEE 1149.1-compliant device be able to generate stimulus patterns and the ASIC be able to capture a signature of its inputs. This means that appropriate macro cells must be used as outputs of the driving device and as inputs to the boundary of the ASIC. These cells require additional space and additional circuitry to be incorporated into each BSC.
Using the IEEE 1149.1-compliant family of testability products from Texas Instruments enables designers to add features previously unachievable in their designs. It is beneficial to test glue logic clusters using existing boundary-scan components that surround the logic cluster. This provides added value to the boundary-scan overhead built into a design's larger devices.
Board-to-board fault detection and isolation within a digital system have historically depended primarily on Built-In Test (BIT) software. This approach is adequate for detecting functional faults on boards assuming that the processor executing BIT software can access the boards installed in the system. Backplane faults typically manifest themselves in these ways:
Many bus faults in today's digital processor environments are so catastrophic in nature that the processor executing BIT can not access the boards installed within the system to isolate the fault.
In much the same way a boundary scan within ASICs allows detection and isolation of etch and solder joint faults on a PWB; surrounding the bus interface of a board with IEEE 1149.1-compliant devices allows detection and isolation of bus and connector faults. By placing IEEE 1149.1-compliant devices in a controlled test mode, each board in turn can drive the backplane bus while the other boards receive the driven logic values.
Broken etch on a motherboard backplane presents similar problems
to that of broken etch on a PWB connecting integrated circuits;
some boards cannot communicate to others past the etch break (see
Figure 7-7). By placing the testability devices on each board
into a controlled test mode, one board at a time can drive logic
data onto the bus while the others are receiving logic data. This
method provides enough conclusive data to detect and isolate the
continuity break.
Figure 7-7. Backplane Open-Circuit Fault
A broken connector pin fault can be detected and isolated in the
same manner as etch breaks; the board with a bad pin is not able
to drive and receive data onto a particular channel on the backplane.
See Figure 7-8.
Figure 7-8. PWB Connector Fault
Termination network open or short to VCC /Ground shows up as a
channel on the backplane that can not be driven to a certain logic
state. The characteristic of this fault could be confused with
a bus contention fault. See Figure 7-9.
Figure 7-9. Backplane Short-To-Ground Fault
Bus contention faults occur when a three-state bus driver is stuck in a functional-enable mode. The BSCs in a controlled mode can be disabled by the test circuitry, thus bypassing the functional-enable control. All of the tests described can be executed offline in a test mode or by Built-in Test (BIT) software interfacing to a IEEE 1149.1-compliant serial scan controller in the system.
Board-to-board fault detection and isolation in a controlled offline test mode and concurrent background BIT execution can be dramatically improved by using boundary-scan testability devices or ASICs with boundary-scan cells within the bus interface circuitry of each board installed in a system. Boundary-scan architecture at the backplane-interface can increase fault isolation by masking some interface logic from the circuitry under test.
Very high density ASIC devices pose severe barriers to all testing, beginning with design verification and continuing with test and verification of the manufactured part.
IEEE 1149.1-based testing can be used for testing and verifying ASIC devices, provided that the design process includes scan-based testing beginning with design specifications. This example cites the development of a vector processor ASIC with 165,000 gates.
The test logic in the vector processor includes internal scan and built-in emulation logic in addition to boundary-scan and the optional INTEST capability. The emulation capability includes control of the processor, implementing RUN, STOP, SINGLE-STEP, and EXAMINE/MODIFY internal registers, and real-time breakpoints.
Design verification, test hardware and test software are developed concurrently with the ASIC. Verification code consists of two types of tests:
ASSET(tm) (Advanced Support System for Emulation and Test) software is used to execute and monitor boundary-scan tests. The tests are used to verify test bus operation, scan path integrity, internal-register access, core-logic operation, and IC-to-IC interconnects. ASSET is used on an IBM PC(tm)-compatible computer and consists of a PC-AT(tm) controller card and controller software. An expanding set of scan-based utilities and special-purpose test programs are written to perform specific tests or trouble-shoot hardware problems. These utilities are developed from the time hardware integration is begun.
In addition to the scan-based tests, embedded test code is developed in microcode to verify instruction set execution, register and memory decode, memory access, and input/output operations. The embedded tests target functional logic and verify at-speed operations.
The vector processor ASIC in the design incorporates extensive internal scan paths and breakpoint logic controlled via the IEEE 1149.1 test bus. Key registers that are accessible via scan include the address and data register files, ALU and multiplier pipeline registers, and the program instruction register.
Initial checkout of the vector processor includes scan path integrity and internal register access using internal scan and boundary scan. The first devices contain nonfunctional microcode RAM therefore an alternate plan is devised to use the IEEE 1149.1 to validate all other circuitry.
The vector processor checkout uses the boundary-scan architecture to perform register reads and writes and simple operations to verify microcode execution. Simple microcode operations are tested by scanning an opcode into the instruction register and clocking the processor using boundary scan.
A test routine is developed in C++ that automates the microcode execution steps. The program reads microcode-object files, scans the instruction into the instruction register, clocks the processor, and reads the program counter to locate the next instruction. As each instruction is executed, the program dumps the accumulator and status registers to allow monitoring of each instruction. This process is repeated for each microcode routine until all microcode is executed and nearly all processor functions are verified using the "bad" vector processors. Many weeks are saved while waiting for new vector processors.
Design verification, hardware test, and software integration represent significant challenges. Anticipating this, many design for test and integration capabilities need to be incorporated into the device to ensure controllability and observability of embedded functions. The IEEE 1149.1 standard provides the primary method for design verification, hardware/software integration, and hardware test.
Test and interaction issues were exaggerated in this example due to the lack of physical access caused by small geometry of the module. Boundary-scan testing saved a significant portion of the design verification effort that would have been required for the less effective conventional physical access methods.
The steady increase in memory density has led to the increased use of high-capacity memory boards in today's electronic systems. It has also encouraged the use of embedded memory within microprocessors, digital signal processors (DSP), and ASICs. As a result, testing of these boards and devices has become more complex. Large-capacity memory boards require very long test execution times for adequate fault detection. Large bus sizes (32 bits) and high bus fanout further complicate the problem of isolating component faults. Embedded memories, which often make up a significant portion of the device area, create additional difficulties due to a lack of test access.
The use of scan-path technologies can simplify the problem of testing large memory arrays within a system or embedded memories within a device. Scan-path devices such as TI's bus interface components can be used to partition large memory device arrays into smaller, more easily testable arrays to increase component fault isolation. In addition, the use of TI's IEEE 1149.1-compliant macro cells within ASIC devices provide controllability and observability of embedded memory that is normally inaccessible. Memory test times can be reduced through the efficient partitioning and testing of several memory arrays (on a board or within a device) in parallel.
Figure 7-10 shows a 256 x 8 memory array, associated bus interface,
and control logic configured to test various memory-pattern-generation
techniques. This configuration allows for explicit read/write
operations using IEEE 1149.1 EXTEST and SAMPLE instructions.
In addition, the components have a BIST capability (controlled
by IEEE 1149.1 instructions) used to perform memory read/write
operations. The test results shown in Table 7-1 compare explicit
scanning in the RAM array address, data, and strobe signal to
using an IEEE 1149.1-instruction-controlled BIST to generate address,
data, and strobe signals automatically at the Test Clock (TCK)
rate of 6.25 MHz.
Figure 7-10. Block Diagram of Simplified Boundary-Scannable
RAM Interface
Table 7-1. Access Rates of IEEE 1149.1 Devices With and Without BIST
Table 7-1 shows that the BIST controlled by IEEE 1149.1 instructions overcomes the limitations of conventional memory testing. Using boundary-scan EXTEST and SAMPLE/PRELOAD solves the direct physical access problem, but it is time consuming. By using BIST circuitry embedded within the functional logic surrounding large memory arrays, IEEE 1149.1 tests can be designed to emulate closely the characteristics and timing speeds of the memory being accessed. TI's bus interface components offer the IEEE 1149.1-controlled BIST functionality required to test memory while providing the electrical signal conditioning and buffering a design engineer typically designs around a microprocessor.
In a similar fashion, TI's family of IEEE 1149.1-compatible cells can be used within an ASIC device to provide access to embedded memory normally inaccessible through external pins. The IEEE 1149.1-compatible cells support the same self-test features as the bus interface devices (PRPG, PSA, Toggle 1/0 modes), which further simplify memory testing. Additional features such as programmable PRPG and PSA taps, built-in comparison logic, maskable PSA/comparison inputs, and bidirectional cells provide even more flexibility in self-test design. These features can be used with a built-in test controller to create an autonomous BIST for the memory array and/or other functions within the device.
The use of IEEE 1149.1 cells in performing read/write tests on
RAM is shown in Figure 7-11. Address sequencing is performed using
the PRPG mode. The PRPG and toggle modes automatically generate
data patterns to be written to the memory cells under test while
the memory write enable is controlled by direct scan. When reading
from memory, data patterns are verified using the comparison logic
in the IEEE 1149.1-compatible cells. This is possible since each
IEEE 1149.1-compatible cell can latch and remember the last data
pattern that was written when configured correctly. During memory
reads, the latched pattern is fed back for comparison with the
data being read. A pass/fail signal for the test can be generated
by combining the comparison outputs of each IEEE 1149.1-compatible
cell.
Figure 7-11. Testing Embedded RAM
A similar testing method can be used when testing Read-Only Memory
(ROM) embedded within a device, as shown in Figure 7-12. During
ROM tests, address sequencing and read enables are controlled
as in Figure 7-11, and the PSA mode is used to compress the data
output into a representative signature. If desired, comparison
logic can be used to compare the calculated signature with a known
good signature to generate a memory pass/fail signal.
Figure 7-12. Testing Embedded ROM
The use of TI's bus interface components and boundary-scan cells provides increased fault detection and isolation capabilities when used to partition large-capacity memory boards and devices with embedded memory. The increased partitioning allows the use of parallel testing and autonomous built-in self test, greatly reducing the overall test execution times normally attributed to memory testing. IEEE 1149.1 bus interface components provide simple replacements for buffers and transceivers that are normally used in memory system design while creating little impact on system performance. TI's boundary cell library is a completely configurable set of test cells that allow the designer to create sophisticated test structures (such as built-in self test for memories) while requiring only a minimal knowledge of test engineering principles.
The backplane environment, which carries many signals in parallel to all the boards, contains certain conditions not found in other test situations. A typical backplane with a complement of boards (such as a computer that uses different accessory boards) may be configured differently for different purposes. In other cases, certain boards may be capable of interacting independent of normal backplane activity, and some boards may include BIST. For maximum usefulness and short test times, a test program must accommodate a partially populated backplane while allowing more than one board to be active at a time.
The IEEE 1149.1 standard was developed to access ICs on a board serially, but it can also be used to access boards installed in a backplane. By making simple hardware modifications to the backplane circuitry, ring or star backplane configurations can be accessed using normal IEEE 1149.1 commands.
In a backplane configured as a ring (see Figure 7-13), all boards
directly receive the TCK and TMS control outputs from a primary
test bus controller (TBC). The scan path is daisy chained between
the TBC's TDO output and TDI input. During a test, the TBC drives
TMS and TCK to scan data through all boards in the backplane,
through the TDO/TDI bus connections. A serial path works only
if all the boards are present and can scan data from their TDI
input to TDO output. A missing or faulty board breaks the path
so the TBC cannot scan data through the backplane.
Figure 7-13. Backplane Ring Configuration
In a backplane star configuration (see Figure 7-14), the TBC drives
TCK and TDI directly to all boards and each board outputs a TDO
signal to the TBC. Each board requires a unique TMS signal from
the TBC and a separate circuit trace for each signal. During testing,
only one board is enabled at a time and only the TMS signal for
that board is active. In a backplane with 50 boards, the TBC needs
50 individual TMS signals, with circuit traces for each. Another
problem is that only one board may be scanned at a time.
Figure 7-14. Backplane Star Configuration
A new serial bus protocol has been developed by Texas Instruments that is interpreted by a TI device called the Addressable Scan Port (ASP) (SN74ABT8996 (1)). This device provides linkage between IEEE 1149.1-compatible boards and a backplane. The ASP becomes the IEEE 1149.1-input bus for each board in the backplane. It intercepts the protocol on the normal incoming IEEE 1149.1 signal wires, allowing it to connect or disconnect its board with the IEEE 1149.1 bus on the backplane. Once connected, the board can communicate using the standard 1149.1-bus protocol.
The ASP protocol is invoked when the IEEE 1149.1 bus is in one of the following four TAP states: Test-Logic-Reset, Run-Test/Idle, Pause-IR, or Pause-DR.
The protocol can address and select any ASP-equipped board in the backplane. After the board is connected to the IEEE 1149.1 bus, the ASP simply passes data through to the bus so normal operation can resume.
(1) SN54ABT8996, SN54ABT8996 10-Bit Addressable Scan Ports Multi-Drop Addressable IEEE 1149.1 (JTAG) TAP Transceivers, Literature Number SCBS489 Texas Instruments, 1994.
Figure 7-15 shows a backplane with ASP devices on each board, allowing individual boards to be configured and active simultaneously.
Figure 7-15. Backplane With ASP-Equipped Boards
For example, if the interconnects between two boards are to be tested, it is necessary to select and scan the first board to output a test pattern, then select the other board to receive the test pattern. The ASP makes it possible to select and scan the second board without resetting the first board. During operation, each pattern of the interconnect test is scanned out of the second board before a new pattern is scanned into the driving board.
Another test may be to select and initiate self-tests in a selected group of backplane boards. The ASP allows BIST to be started on each board and left running while other board tests are initialized. Each board is then polled to read the test results, one board at a time.
The special problems associated with backplane testing can be accommodated when the SN74ABT8996 Addressable Scan Port is added to individual boards.
Field testing can be simplified if equipment is configured to take advantage of embedded IEEE 1149.1 functions.
TI's SN74ACT8990(2)Test Bus Controller (TBC) can be embedded in system circuitry to provide autonomous IEEE 1149.1-based testing. A licensable, embeddable "C" source code product called Scan Engine, which includes test vector translators, is available to simplify embedded boundary-scan tests.
The host interface on the TBC consists of a 16-bit data bus (DATA15-0), 5-bit address bus (ADRS4-0), a read strobe (/RD) and a write strobe (/WR). Twenty-four 16-bit internal registers are accessible by the host processor.
Both port 0 and port 1 share a common TDO and TCK. The 'ACT8990 has separate TDI pins for ports 0 and 1, so that the return serial data from each scan path remains isolated.
(2) SN54ACT8990, SN74ACT8990 Test Bus Controllers, Literature Number SCAS190B, Texas Instruments 1994.
The 'ACT8990 has two separate IEEE 1149.1-compliant interface ports, only one of which Scan Engine software can access at a given time. Port 0 consists of three signals: TMS0, TDI0, TDO. Port 1 signals are: TMS1, TDI1, TDO.
This allows an active buffer/driver to be used between TDO of the last scannable device and the TDI input pins. TDO is common for both ports 0 and 1. Port selection is controlled by which TMS signal is activated.
The 'ACT8990 has a pin designated TOFF*. This pin controls all output pins of the 'ACT8990. When asserted (logic low), all 'ACT8990 I/O pins and output pins are forced to the high-impedance state.
By placing the outputs of the 'ACT8990 in high-impedance state, the IEEE 1149.1-compliant interface is disabled. This allows an external IEEE 1149.1-compliant controller (such as the ASSET Interface Pod) to take over the scan bus.
A host processor executing embedded Scan Engine software needs three primary hardware resources:
It should be noted that the SBSF stimulus data could either be downloaded into RAM or be permanently programmed into ROM/EPROM.
The SN74ACT8990 Test Bus Controller offers the designer of high-reliability equipment a way to embed automatic IEEE 1149.1-compliant test circuitry into products. Scan Engine provides an easy way to control the SN74ACT8990 in an embedded system. The solution discussed here maintains IEEE 1149.1-compatibility and access to test vectors developed during design verification. The result is continuous quality assurance with direct traceability to development data.
When new ASICs or boards come from the manufacturing line, the first concern is that the devices work as designed. High-density ASICs and multi-layer PWBs with surface mount devices can't be adequately tested without boundary-scan testing.
Use boundary-scan techniques and tools on products designed with 1149.1-1990-compatible components.
Figure 7-16 summarizes an efficient verification process using
BSDL supplied by manufacturers of IEEE 1149.1-compatible ICs and
HSDL developed for the ASICs and PWB.
Figure 7-16. General Boundary-Scan Test
Automated-assembly verification depends on getting BSDL or HSDL
descriptions for IEEE 1149.1-compatible devices from the manufacturer
and developing corresponding HSDL for modules, boards, and systems.
Figure 7-17 shows the flow that verifies a correct scan path and
interconnections between boundary-scan cells.
A
Figure 7-17. Assembly-Verification Flow
Devices that pass assembly verification must then be tested for functionality.
Functional verification begins with IC testing followed by virtual
component or cluster testing and system verification. These flows
and the tools involved are shown in Figure 7-18.
Figure 7-18. Automated Functional Verification and Fault
Detection
No matter which flow is used, the goal is to reuse data whenever possible. For functional verification we want to reuse any serial or parallel vectors developed in the CAE system; those vectors become a pass/fail test. When CAE vectors are not available, ASSET supports test stimulus development approaches such as vector recording, macros, and C++ programs.
All functional tests highlight failures down to the vector level. Knowing which vector failed can reduce the time spent in interactive testing to isolate the problem to a device, register, or pin.
Figure 7-19 shows how faults in units failing previous tests can
be isolated using specialized software tools, the ASSET Debugger
and Scan Analyzer.
Figure 7-19. Interactive Verification and Fault Isolation
Design verification and fault isolation processes are greatly enhanced when a full suite of boundary-scan tools and techniques are used.
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