The concern most often voiced by Application Specific Integrated Circuit (ASIC) users is that of testability. This chapter is intended to provide an understanding of ASIC testability that can be used for developing test strategies when designs are being initiated.
Designing testability into any circuit affects the hardware to some degree. Additional logic will probably have to be added. This additional logic increases the amount of silicon required to implement the design. The savings from enhanced testability do not usually show up until the cycle time and testing cost of the circuit and its end system are analyzed.
Fault simulation is an important part of designing for testability. This technique enables you to evaluate your test patterns to determine whether these patterns detect faults. Faults may occur during either the design-tooling stage or the circuit-fabrication stage. A fault simulator uses fault models, such as a node shorted to power (stuck-at-one) or a node shorted to ground (stuck-at-zero), and compares the response of a fault-free circuit with the response of a faulty circuit. If the response of the fault-free circuit is different than the response of the faulty circuit, then the test patterns have detected the fault.
By faulting all the nodes in the circuit, the fault simulator produces the test pattern fault grade or fault coverage. The fault coverage is the percentage of faults detected among the total faults. The higher the fault coverage, the better the test pattern set separates a faulty circuit from a fault-free circuit. After determining which faults have not been detected by the current set of test patterns, you can generate additional test patterns to detect those faults.
Adoption of design-for-test principles early in the design process ensures the maximum testability for the minimum effort. These guidelines emphasize that test is a part of the design flow, not a process that is done at the end of the design cycle.
Three basic elements must come together to make a successful ASIC circuit:
Most engineers involved in the design of ASIC devices are familiar with the trade-offs between gate arrays, standard cells, and full custom devices. They are also familiar with the vendor selection process. This aspect of test capability and testability is often overlooked.
Testability could be ignored when typical designs were only a few thousand gates. These designs were implemented first and then turned over to a test engineer or to a vendor to create a test program for production. As design complexities increased, this approach to testing became futile. Successful high-density ASIC design and manufacturing demand that circuits be put together with testability incorporated into the design process.
Although testability imposes additional constraints in the design phase, design verification and test can be unmanageable if ignored until the design is completed and testability is handled as a postdesign insertion. In fact, the design constraints are overwhelmingly balanced by improved testability, which adds value to the device throughout manufacturing and system life.
Test cost, as it relates to time, is a simple calculation. Most commercial testers cost between $2 million and $3 million. Under normal circumstances, the tester depreciation, plant, operator, and support personnel costs are between 10 and 20 cents per test second.
Brute-force test approaches often generate a large number of test patterns. Since test patterns are run at multiple power supply values and possibly at multiple temperatures, inefficient pattern sets can severely impact the test costs of a complex ASIC device.
Surveys indicate that 40 percent of the development cycle time for an ASIC device is required for test insertion and test pattern generation. This figure is expected to increase as device complexity increases. The intent of a design-for-test strategy is to achieve high fault detection test programs in reduced time (Figure 4-1). The obvious cycle-time reductions result from designed-in testability (elimination of iterative redesigns resulting from poor design practices), and from automatic test pattern generation (ATPG).
Figure 4-1. Fault Grade Versus Development Time
Figure 4-2 shows the economic relationship between time-to-market
and system manufacturing and field maintenance costs. Point 1
represents the case where market entry timing forces a constraint
on the development time. Since 40 percent of this time is expended
in inserting testability, the temptation is to rush to market
with devices that are not completely testable or tested. The result
is a higher than desirable manufacturing and field-maintenance
cost. Point 2 represents the case where DFT and ATPG techniques
are employed to develop devices that are completely tested. This
situation allows an economic optimum that is more favorable to
long-term manufacturing and maintenance costs.
Figure 4-2. Economic Trade Off for a Testable Design
A less obvious result of a DFT strategy is the reduction of debug time. You, as designer, must make certain assumptions about system requirements. Often a new device does not work in the system environment and requires debugging. If the device is designed for controllability and observability access, the debugging process is enhanced. Conversely, if these two features are overlooked, debugging and manufacturing can be significantly harder to accomplish, if not impossible. Oscilloscopes and logic analyzers are not very effective in debugging systems utilizing complex ASIC devices in a surface-mount environment.
Figure 4-3 shows the trade-off between time-to-market and manufacturing and field-maintenance costs. The horizontal factor on this figure is fault coverage. The relationship between fault coverage and device defect level is well documented.
Figure 4-3 is a plot of the relationship modelled by T. W. Williams for fault coverages of 90 percent or greater.
Where:
Figure 4-3. Defect Level Versus Fault Coverage
To explore the Williams model briefly, assume that the ASIC vendor has a silicon and assembly process yield that is 70 percent. If the fault grade of the test program is also 70 percent, the defect level is projected to be 10.1 percent or 101,000 ppm (This is outside the limits of the chart and was calculated.). At a fault grade of 90 percent, the defect level is projected to be 3.5 percent or 35,000 ppm.
A study of the model shows that the process yield becomes an insignificant term when the fault coverage of the test program is very close to 100 percent.
Motorola and Delco performed a study in 1980 that supports the
Williams model. Their experimental results are shown in Figure
4-4. A fault coverage of 99.9 percent was required to obtain defect
levels in the range of 100 ppm.
Figure 4-4. Motorola and Delco Study Results
Figure 4-5 shows the maximum allowable ASIC defect rate to achieve
a goal PCB defect rate as a function of the number of ASIC devices
per board assembly. Note that for multiple-device PCB designs,
a goal of 500 ppm requires ASIC defect levels in the range of
100 to 200 ppm.
Figure 4-5. ASIC ppm Versus PCB ppm Rate
Theoretical and experimental studies conclude that a high-fault-grade test-pattern set is required for low defect level ASIC devices. This type of pattern set is nearly impossible to obtain through brute force. The requirements for a high-fault-grade pattern set are:
As stated earlier, a design-for-test strategy has performance and area costs. Now the cost of new tools has been added. Benefits such as lower test costs and reduced time to market have been mentioned. These benefits are real, but often hard to quantify. Reduced cost of ownership is another major benefit and is easy to quantify.
Figure 4-6 shows what is commonly referred to as the "cost-of-ownership, order-of-magnitude relationship". It shows that each company has a cost associated with finding a defect in a packaged device before it has entered the assembly process. This cost can be calculated easily. The cost of finding a defective device after assembly onto a PCB is an order of magnitude more than before assembly. This continues until the cost to discover a defective device in a system at a customer's site is three orders of magnitude higher than that of discovery before assembly on to a PCB. The lowest cost of ownership is to find defective units before they are shipped from the vendor.
The previous discussions lead to the conclusion that the lowest cost of ownership can be obtained by providing the ASIC vendor with an efficient, high-fault-detection set of test vectors. These DFT methodologies provide lower cost of ownership with the added benefit of reduced time to market.
The following strategies step you through the process of design for test.
1. Select a technology.
2. Commit to testability design practices.
3. Establish a fault-grade requirement.
4. Decide if IEEE Std 1149.1 will be a system requirement.
5. Select an ASIC testability approach based on gate density.
6. Choose structured tools.
7. Establish a diagnostic functional-pattern set to expedite debug.
8. Generate high fault-grade test patterns.
9. Simulate test patterns and timing.
Figure 4-7 contains a flow chart that steps through the design-for-test
process.
Figure 4-7. Testability Development Flow
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