LIBRARY ieee;  USE ieee.std_logic_1164.all;

architecture behavior of dff is
begin
   p1 : process (set, reset, clk) is
   begin
      if set = '1' and reset = '1' then
         q <= 'X';
      elsif set = '1' and reset = '0' then
         q <= '1';
      elsif set = '0' and reset = '1' then
         q <= '0';
      elsif set = '0' and reset = '0' and rising_edge(clk) then
         q <= d;
      end if;
   end process p1;
end architecture behavior;

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