-- EE 301 Problem 5-18
-- Develop a behavioral model for a D-latch with a 
-- clock-to-output propagation delay of 3 ns and a
-- data-to-output propagation delay of 4 ns

LIBRARY ieee;  USE ieee.std_logic_1164.all;

architecture behavior of d_latch is
   constant clocked_time : time := 3 ns;
   constant data_time : time := 4 ns;
begin
   action : process (d, clk ) is
   begin
      if rising_edge (clk) then
         q <= d after clocked_time;
      elsif clk = '1' or clk = 'H' then
         q <= d after data_time;
      end if;
   end process action;
end architecture behavior;


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