-- VHDL configuration for component timer

CONFIGURATION cfg_timer_behav OF timer IS 
   FOR struct -- architecture of timer
      FOR ALL : bcd_counter 
         USE ENTITY work.bcd_counter(spec);    
      END FOR;
      FOR ALL : six_counter 
         USE ENTITY work.six_counter(spec);
      END FOR;
      FOR ALL : d_latch 
         USE ENTITY work.d_latch;
      END FOR;
   end for;
end cfg_timer_behav;


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