// Verilog code for 4 port bus arbiter circuit
`timescale 1ns/100ps
module arbiter (request, grant, clock);
input [3:0] request;
input clock;
output [3:0] grant;
reg [3:0] grant;
reg found;
integer i;
initial i = 0;
always
begin
@(negedge clock);
#20;
found = 0;
for (i=3; i>=0; i=i-1)
if (request[i]==0) grant[i] = 0;
if (grant == 4'd0)
for (i=3; i>=0; i=i-1)
if (request[i] && found == 0) begin
grant[i] = 1;
found = 1;
end
end
endmodule
// Verilog test bench and stimulus for arbiter
`timescale 10ns/1ns
module test_arbiter;
reg clk;
reg [3:0] r;
wire [3:0] g;
integer delays [3:0], usage [3:0];
arbiter u1 (r, g, clk);
initial begin
delays [3] = 400; delays [2] = 300;
delays [1] = 1500; delays [0] = 800;
usage [3] = 300; usage [2] = 400;
usage [1] = 600; usage [0] = 100;
clk = 0; r = 0;
#2000 $stop;
end
always #50 clk = ~clk;
always begin
#(delays[3]) r[3] = 1;
@(posedge g[3]);
#(usage[3]);
@(negedge clk) r[3] = 0;
end
always begin
#(delays[2]) r[2] = 1;
@(posedge g[2]);
#(usage[2]);
@(negedge clk) r[2] = 0;
end
always begin
#(delays[1]) r[1] = 1;
@(posedge g[1]);
#(usage[1]);
@(negedge clk) r[1] = 0;
end
always begin
#(delays[0]) r[0] = 1;
@(posedge g[0]);
#(usage[0]);
@(negedge clk) r[0] = 0;
end
endmodule
// Verilog test bench and stimulus for d_flipflop
`timescale 10ns/1ns
module test_d_flipflop;
reg d;
reg c;
wire q, qb;
d_flipflop u1 (d, c, q, qb);
initial
begin
c = 1'b0; d= 1'b0; // #200; $stop;
#10 d = 1; #10 c = 1; #10 c = 0; #1 d = 0;
#10 c = 1; #0.3 d = 1; #10 c = 0; #2 d = 0;
#11 c = 1; #09 d = 1; #12 c = 0; #2 d = 0;
#11 d = 1; #09 c = 1; #12 c = 0; #2 d = 0;
#7 $stop;
end
endmodule
`timescale 1ns/100ps
module d_flipflop (d, c, q, qb);
input d, c;
output q, qb;
reg q, qb;
parameter delay1 = 4, delay2 = 5;
always @(posedge c) begin
#delay1 q = d;
#(delay2 - delay1) qb = ~ d;
end
endmodule
`timescale 1ns/100ps
module d_flipflop (d, c, q, qb);
input d, c;
output q, qb;
reg q, qb;
parameter delay1 = 4, delay2 = 5;
always @(posedge c) begin
q = #delay1 d;
qb = #(delay2 - delay1) ~ d;
end
endmodule
`timescale 1ns/100ps
module d_flipflop (d, c, q, qb);
input d, c;
output q, qb;
reg q, qb;
parameter delay1 = 4, delay2 = 5;
always @(posedge c) begin
fork
#delay1 q = d;
#delay2 qb = ~ d;
join
end
endmodule
`timescale 1ns/100ps
module d_flipflop (d, c, q, qb);
input d, c;
output q, qb;
reg q, qb;
parameter delay1 = 4, delay2 = 5;
always @(posedge c) begin
fork
q = #delay1 d;
qb = #delay2 ~d;
join
end
endmodule
`timescale 1ns/100ps
module d_flipflop (d, c, q, qb);
input d, c;
output q, qb;
reg q, qb;
parameter delay1 = 4, delay2 = 5;
always @(posedge c) begin
q <= #delay1 d;
qb <= #delay2 ~ d;
end
endmodule
`timescale 1ns/100ps
module d_sr_flipflop (d, set, rst, clk, q, qb);
input d, set, rst, clk;
output q, qb;
reg q, qb, state;
parameter sq_delay = 6, rq_delay = 6, cq_delay = 6;
always @(posedge clk or posedge rst or posedge set) begin
if (set) begin
state = #sq_delay 1;
end else if (rst) begin
state = #rq_delay 0;
end else if (clk) begin
state = #cq_delay d;
end
end
always @(state) begin
q = state;
qb = ~state;
end
endmodule
// Verilog test bench and stimulus for d_sr_flipflop
`timescale 10ns/1ns
module test_d_sr_flipflop;
reg d, set, rst, clk;
wire q, qb;
d_sr_flipflop u1 (d, set, rst, clk, q, qb);
initial begin
clk = 0; d= 0; set = 0; rst = 0;
end
always clk = #4 ~clk;
always d = #7 ~d;
initial begin
#25 set = 1; #11 set = 0; #15 rst = 1; #11 rst = 0;
#10 $stop;
end
endmodule
`timescale 1ns/100ps
module d_sr_flipflop (d, set, rst, clk, q, qb);
input d, set, rst, clk;
output q, qb;
reg q, qb;
parameter sq_delay = 6, rq_delay = 6, cq_delay = 6;
always @(posedge clk or posedge rst or posedge set) begin
if (set) begin
q <= #sq_delay 1;
qb <= #sq_delay 0;
end else if (rst) begin
q <= #rq_delay 0;
qb <= #rq_delay 1;
end else if (clk) begin //can remove if (clk)
q <= #cq_delay d;
qb <= #cq_delay ~d;
end
end
endmodule
`timescale 1ns/100ps
module d_sr_flipflop (d, set, rst, clk, q, qb);
input d, set, rst, clk;
output q, qb;
reg q, qb, state;
parameter sq_delay = 6, rq_delay = 6, cq_delay = 6;
always @(posedge clk or posedge rst or posedge set) begin
if (set) begin
state = 1;
end else if (rst) begin
state = 0;
end else if (clk) begin
state = d;
end
#((sq_delay+rq_delay+cq_delay)/3) q = state;
qb <= ~q;
end
endmodule
`timescale 1ns/100ps
module d_sr_flipflop (d, set, rst, clk, q, qb);
input d, set, rst, clk;
output q, qb;
reg q, qb, state;
parameter sq_delay = 6, rq_delay = 6, cq_delay = 6;
parameter t_setup = 4, t_hold = 4;
specify
$setup (d, posedge clk, t_setup);
$hold (posedge clk, d, t_hold);
endspecify
always @(posedge clk or posedge rst or posedge set) begin
if (set) begin
state = #sq_delay 1;
end else if (rst) begin
state = #rq_delay 0;
end else if (clk) begin //can skip clk check
state = #cq_delay d;
end
end
always @(state) begin
q = state;
qb = ~state;
end
endmodule
`timescale 1ns/100ps
module d_sr_flipflop (d, set, rst, clk, q, qb);
input d, set, rst, clk;
output q, qb;
reg q, qb;
parameter sq_delay = 6, rq_delay = 6, cq_delay = 6;
parameter t_setup = 4, t_hold = 4;
specify
(clk *> q, qb) = cq_delay;
(set *> q, qb) = sq_delay;
(rst *> q, qb) = rq_delay;
$setup (d, posedge clk, t_setup);
$hold (posedge clk, d, t_hold);
endspecify
always @(posedge clk or posedge rst or posedge set) begin
if (set) begin
q = 1; qb = 0;
end else if (rst) begin
q = 0; qb = 1;
end else if (clk) begin //if (clk) not essential
q = d; qb = ~d;
end
end
endmodule
`timescale 1ns/100ps
module moore_detector (x, clk, z);
input x, clk;
output z;
reg [2:0] current;
parameter [1:0]
reset = 0,
got1 = 1,
got10 = 2,
got101 =3,
got1011 =4;
initial current = reset;
always @(posedge clk)
case (current)
reset:
if (x==1) current = got1;
else current = reset;
got1:
if (x==0) current = got10;
else current = got1;
got10:
if (x==1) current = got101;
else current = reset;
got101:
if (x==1) current = got1011;
else current = got10;
got1011:
begin
if (x==1) current = got1;
else current = got10;
end
endcase
assign z = (current == got1011) ? 1 : 0;
endmodule
// Verilog test bench and stimulus for moore_detector
`timescale 10ns/1ns
module test_moore_detector;
reg x;
reg clk;
wire z;
moore_detector u1 (x, clk, z);
initial
begin
x = 0; clk = 0; #70; $stop;
end
always #4 x = ~x;
always #1.5 clk = ~clk;
endmodule
`timescale 1ns/100ps
module moore_detector (x, clk, z);
input x, clk;
output z;
reg [2:0] current;
reg z;
parameter [1:0]
reset = 0,
got1 = 1,
got10 = 2,
got101 =3,
got1011 =4;
initial current = reset;
always @(posedge clk)
case (current)
reset:
begin
if (x==1) current = got1;
else current = reset;
z = 0;
end
got1:
begin
if (x==0) current = got10;
else current = got1;
z = 0;
end
got10:
begin
if (x==1) current = got101;
else current = reset;
z = 0;
end
got101:
begin
if (x==1) begin
current = got1011; z = 1;
end else begin
current = got10; z = 0;
end
end
got1011:
begin
if (x==1) current = got1;
else current = got10;
z = 0;
end
endcase
endmodule
`timescale 1ns/100ps
module moore_detector (x, clk, z);
input x, clk;
output z;
reg [2:0] current;
reg z;
parameter
reset = 0,
got1 = 1,
got10 = 2,
got101 =3,
got1011 =4;
initial current = reset;
always @(posedge clk) begin
case (current)
reset:
if (x==1) current = got1;
else current = reset;
got1:
if (x==0) current = got10;
else current = got1;
got10:
if (x==1) current = got101;
else current = reset;
got101:
if (x==1) current = got1011;
else current = got10;
got1011:
if (x==1) current = got1;
else current = got10;
endcase
if (current == got1011) z = 1; else z = 0;
end
endmodule
UNDER CONSTRUCTION
`timescale 1ns/100ps
module onehot_moore_detector (x, clk, z);
input x, clk;
output z;
reg reset, got1, got10, got101, got1011;
reg z;
initial {reset, got1, got10, got101, got1011} = 5'b10000;
always @(posedge clk)
if (reset)
begin
if (x==1) current = got1;
else current = reset;
z = 0;
end
got1:
begin
if (x==0) current = got10;
else current = got1;
z = 0;
end
got10:
begin
if (x==1) current = got101;
else current = reset;
z = 0;
end
got101:
begin
if (x==1) begin
current = got1011; z = 1;
end else begin
current = got10; z = 0;
end
end
got1011:
begin
if (x==1) current = got1;
else current = got10;
z = 0;
end
endcase
endmodule
`timescale 1ns/100ps
module asynch_reset_detector (x, r, clk, z);
input x, r, clk;
output z;
reg [1:0] nxt, present;
reg z;
parameter
a = 0,
b = 1,
c = 2;
initial nxt = a;
always @(posedge clk or posedge r)
if (r==1) present = a;
else present = nxt;
always @(present or x) begin
z = 0;
case (present)
a:
if (x==0) nxt = a;
else nxt = b;
b:
if (x==0) nxt = c;
else nxt = b;
c:
if (x==0) nxt = a;
else nxt = b;
default:
nxt = a;
endcase
if (present == c && x == 1) z = 1;
end
endmodule
// Verilog test bench and stimulus for asynch_reset_detector
`timescale 10ns/1ns
module test_synch_asynch_reset_detector;
reg x, r, clk;
wire z_async, z_sync;
asynch_reset_detector u1 (x, r, clk, z_async);
synch_reset_detector u2 (x, r, clk, z_sync);
initial begin
x = 0; clk = 0; #99; $stop;
end
initial begin
r = 0;
#6 r = 1; #6 r = 0;
#66 r = 1; #6 r = 0;
end
always #4 x = ~x;
always #1.5 clk = ~clk;
endmodule
`timescale 1ns/100ps
module synch_reset_detector (x, r, clk, z);
input x, r, clk;
output z;
reg [1:0] nxt, present;
reg z;
parameter
a = 0,
b = 1,
c = 2;
initial nxt = a;
always @(posedge clk)
if (r==1) present = a;
else present = nxt;
always @(present or x) begin
z = 0;
case (present)
a:
if (x==0) nxt = a;
else nxt = b;
b:
if (x==0) nxt = c;
else nxt = b;
c:
if (x==0) nxt = a;
else nxt = b;
default:
nxt = a;
endcase
if (present == c && x == 1) z = 1;
end
endmodule
`timescale 1ns/100ps
`define BPS 10000
module serial2parallel (serial, received, dataready,
overrun, frame_error, parallel_out);
input serial, received;
output dataready, overrun, frame_error;
output [7:0] parallel_out;
reg dataready, overrun, frame_error;
reg [7:0] parallel_out;
reg [7:0] buff;
initial begin
frame_error = 0;
dataready = 0;
overrun = 0;
parallel_out = 1'b0;
end
parameter
half_bit = 1E9/(`BPS*2.0),
full_bit = 1E9/`BPS;
always begin
@(negedge serial);
#half_bit;
repeat(8) #full_bit buff = {serial, buff[7:1]};
#full_bit;
if (serial == 0) begin
frame_error = 1;
@(posedge serial);
end else begin
frame_error = 0;
dataready = 1;
parallel_out = buff;
@(posedge received) @(negedge received);
dataready = 0;
end
end
always begin
@(dataready);
if (dataready==1) begin
@(negedge serial) if (dataready==1) overrun = 1;
end else
overrun = 0;
end
endmodule
`timescale 10ns/1ns
`define BPS 10000
module test_serial2parallel;
reg serial, received;
wire dataready, overrun, frame_error;
wire [7:0] parallel_out;
parameter fb = 1E8/`BPS;
serial2parallel u1 (serial, received, dataready,
overrun, frame_error, parallel_out);
initial begin
serial = 1;
#(02*fb) serial = 0; #(01*fb) serial = 1; #(01*fb) serial = 0;
#(02*fb) serial = 1; #(14*fb) serial = 0; #(03*fb) serial = 1;
#(02*fb) serial = 0; #(01*fb) serial = 1; #(01*fb) serial = 0;
#(01*fb) serial = 1; #(05*fb) serial = 0; #(10*fb) $stop;
end
initial begin
received = 0;
#(160000) received = 1;
#(10) received = 0;
#(190000) received = 1;
#(10) received = 0;
end
endmodule
// interface circuit for nibble receive, word transmitter
`timescale 1ns/100ps
module system_i (in_data, out_data, in_ready, out_received,
in_received, out_ready);
input [3:0] in_data;
input in_ready, out_received;
output [15:0] out_data;
output out_ready, in_received;
reg [15:0] out_data;
reg out_ready, in_received;
reg [3:0] word_buffer [3:0];
reg buffer_full, buffer_picked;
reg [1:0] i;
initial begin i = 0; end
always begin
@(posedge in_ready);
word_buffer [i] = in_data;
if (i==3) begin
buffer_full = 1;
@(posedge buffer_picked);
buffer_full = 0;
i = 0;
end else i = i + 1;
in_received = 1;
@(negedge in_ready);
in_received = 0;
end
always begin
wait(buffer_full);
out_data = {word_buffer [3],
word_buffer [2],
word_buffer [1],
word_buffer [0]};
buffer_picked = 1;
@(negedge buffer_full);
buffer_picked = 0;
out_ready = 1;
@(posedge out_received);
out_ready = 0;
end
endmodule
// Verilog test bench and stimulus for system_interface
`timescale 10ns/1ns
module test_system_interface;
reg [3:0] a_data;
reg a_ready;
wire a_received;
wire [15:0] b_data;
wire b_ready;
reg b_received;
integer i, seed;
system_i u1 (a_data, b_data, a_ready, b_received, a_received, b_ready);
initial begin
for (i=1; i <= 15; i = i+ 1) seed <= #(i*3) i;
a_ready = 0; b_received = 0;
#42 $stop;
end
// this models system_a
always begin
a_data = $random (seed);
repeat (4) begin
#2 a_data = {~a_data [0], a_data [3:1]};
a_ready = 1;
@(posedge a_received);
#1 a_ready = 0;
end
end
// this models system_b
always begin
@(posedge b_ready);
#1 b_received = 1;
@(negedge b_ready);
#2 b_received = 0;
end
endmodule
// Verilog code for two phase clock generation
`timescale 1ns/100ps
module two_phase;
reg c1, c2;
always
begin
wait (c1==1)
wait (c1==0)
#10
c2 = 1;
#480;
c2 = 0;
end
initial begin c1 = 1; #4000 $stop; end
always #500 c1 = ~c1;
endmodule