`timescale 1ns/100ps

module dcd_3_to_8 (adr, so);

input [2:0] adr;

output [7:0] so;

assign #(5,7)

so = adr === 3'b000 ? 8'b00000001 :

adr === 3'b001 ? 8'b00000010 :

adr === 3'b00Z ? 8'b00000010 :

adr === 3'b010 ? 8'b00000100 :

adr === 3'b0Z0 ? 8'b00000100 :

adr === 3'b011 ? 8'b00001000 :

adr === 3'b01Z ? 8'b00001000 :

adr === 3'b0Z1 ? 8'b00001000 :

adr === 3'b0ZZ ? 8'b00001000 :

adr === 3'b100 ? 8'b00010000 :

adr === 3'b101 ? 8'b00100000 :

adr === 3'b10Z ? 8'b00100000 :

adr === 3'bZ01 ? 8'b00100000 :

adr === 3'bZ0Z ? 8'b00100000 :

adr === 3'b110 ? 8'b01000000 :

adr === 3'b1Z0 ? 8'b01000000 :

adr === 3'bZ10 ? 8'b01000000 :

adr === 3'bZZ0 ? 8'b01000000 :

adr === 3'b111 ? 8'b10000000 :

adr === 3'b11Z ? 8'b10000000 :

adr === 3'b1Z1 ? 8'b10000000 :

adr === 3'b1ZZ ? 8'b10000000 :

adr === 3'bZ11 ? 8'b10000000 :

adr === 3'bZ1Z ? 8'b10000000 :

adr === 3'bZZ1 ? 8'b10000000 :

adr === 3'bZZZ ? 8'b10000000 :

8'BXXXXXXXX;

endmodule

// Verilog test bench and stimulus for dcd_3_to_8

`timescale 10ns/1ns

module test_dcd_3_to_8;

wire [7:0] so;

reg [2:0] adr;

dcd_3_to_8 u1 (adr, so);

initial

begin

adr = 3'b010;

#50;

adr = 3'bZ10;

#50;

adr = 3'b100;

#50;

adr = 3'b0Z0;

#50;

adr = 3'bZ10;

#50;

adr = 3'b01Z;

#50;

adr = 3'b000;

#50;

adr = 3'bZZ1;

#50;

adr = 3'bZ10;

#50;

adr = 3'b01Z;

#50;

adr = 3'b110;

#50;

adr = 3'b11Z;

#50;

adr = 3'b0Z0;

#50;

adr = 3'bZ1Z;

#50;

adr = 3'b111;

#50;

end

endmodule`timescale 1ns/100ps

module dcd_3_to_8 (adr, so);

input [2:0] adr;

output [7:0] so;

assign #(5,7)

so = adr === 3'b000 ? 8'b00000001 :

adr === 3'b001 ? 8'b00000010 :

adr === 3'b00Z ? 8'b00000010 :

adr === 3'b010 ? 8'b00000100 :

adr === 3'b0Z0 ? 8'b00000100 :

adr === 3'b011 ? 8'b00001000 :

adr === 3'b01Z ? 8'b00001000 :

adr === 3'b0Z1 ? 8'b00001000 :

adr === 3'b0ZZ ? 8'b00001000 :

adr === 3'b100 ? 8'b00010000 :

adr === 3'b101 ? 8'b00100000 :

adr === 3'b10Z ? 8'b00100000 :

adr === 3'bZ01 ? 8'b00100000 :

adr === 3'bZ0Z ? 8'b00100000 :

adr === 3'b110 ? 8'b01000000 :

adr === 3'b1Z0 ? 8'b01000000 :

adr === 3'bZ10 ? 8'b01000000 :

adr === 3'bZZ0 ? 8'b01000000 :

adr === 3'b111 ? 8'b10000000 :

adr === 3'b11Z ? 8'b10000000 :

adr === 3'b1Z1 ? 8'b10000000 :

adr === 3'b1ZZ ? 8'b10000000 :

adr === 3'bZ11 ? 8'b10000000 :

adr === 3'bZ1Z ? 8'b10000000 :

adr === 3'bZZ1 ? 8'b10000000 :

adr === 3'bZZZ ? 8'b10000000 :

8'BXXXXXXXX;

endmodule

`timescale 1ns/100ps

module de_flipflop (d, e, c, q, qb);

input d, e, c;

output q, qb;

reg q, qb;

parameter delay1 = 4, delay2 = 5;

always @(posedge c) q = #delay1 e ? d : q;

always @(posedge c) qb = #delay2 e ? ~d : qb;

endmodule

// Verilog test bench and stimulus for de_flipflop

`timescale 10ns/1ns

module test_de_flipflop;

reg d, e, c;

wire q, qb;

de_flipflop u1 (d, e, c, q, qb);

initial

begin

c = 1'b0; d= 1'b0;

#10 e = 1; #91 e = 0;

#60 e = 1; #91 $stop;

end

always #10 c = ~ c;

always #13 d = ~ d;

endmodule

`timescale 1ns/100ps

module detector (x, clk, z);

input x, clk;

output z;

reg [1:0] current;

parameter [1:0] reset = 0,

got1 = 1,

got10 = 2,

got101 =3;

initial current = reset;

always @(posedge clk) current =

current == reset ? (x == 1 ? got1 : reset) :

current == got1 ? (x == 0 ? got10 : got1) :

current == got10 ? (x == 1 ? got101 : reset) :

current == got101 ? (x == 1 ? got1 : got10) : reset;

assign z = current == got101 ? (x == 1 ? 1 : 0) : 0;

endmodule

// Verilog test bench and stimulus for detector

`timescale 10ns/1ns

module test_detector;

reg x;

reg clk;

wire z;

detector u1 (x, clk, z);

initial

begin

x = 0; clk = 0; #70; $stop;

end

always #4 x = ~x;

always #1.5 clk = ~clk;

endmodule

`timescale 1ns/100ps

module d_flipflop (d, c, q, qb);

input d, c;

output q, qb;

reg q, qb; // default is wire, use reg in concurrent statements

parameter delay1 = 4, delay2 = 5;

always @(posedge c) #delay1 q = d;

always @(posedge c) #delay2 qb = ~ d;

endmodule

// Verilog test bench and stimulus for d_flipflop

`timescale 10ns/1ns

module test_d_flipflop;

reg d;

reg c;

wire q, qb;

d_flipflop u1 (d, c, q, qb);

initial

begin

c = 1'b0; d= 1'b0; // #200; $stop;

#10 d = 1; #10 c = 1; #10 c = 0; #1 d = 0;

#10 c = 1; #0.3 d = 1; #10 c = 0; #2 d = 0;

#11 c = 1; #09 d = 1; #12 c = 0; #2 d = 0;

#11 d = 1; #09 c = 1; #12 c = 0; #2 d = 0;

#7 $stop;

end

endmodule

`timescale 1ns/100ps

module d_flipflop (d, c, q, qb);

input d, c;

output q, qb;

reg q, qb;

parameter delay1 = 4, delay2 = 5;

always @(posedge c) q = #delay1 d;

always @(posedge c) qb = #delay2 ~ d;

endmodule

`timescale 1ns/100ps

module mux_8_to_1 (i7, i6, i5, i4, i3, i2, i1, i0,

s7, s6, s5, s4, s3, s2, s1, s0, z );

input i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0;

output z;

assign z =

s7 == 1 ? i7 :

s6 == 1 ? i6 :

s5 == 1 ? i5 :

s4 == 1 ? i4 :

s3 == 1 ? i3 :

s2 == 1 ? i2 :

s1 == 1 ? i1 :

s0 == 1 ? i0 :

0;

endmodule

// Verilog test bench and stimulus for mux_8_to_1

`timescale 10ns/1ns

module test_mux_8_to_1;

wire z;

reg i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0;

mux_8_to_1 u1 (i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0, z);

initial

begin

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00000000;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b01000000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b01000000;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b01000000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b01100000;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b01000000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00010000;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b01010000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00010000;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b01000000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00001000;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b00000000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00000100;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b01000100;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00000010;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b00100000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00000001;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b10000001;

#50;

end

endmodule`timescale 1ns/100ps

module mux_8_to_1 (i7, i6, i5, i4, i3, i2, i1, i0,

s7, s6, s5, s4, s3, s2, s1, s0, z );

input i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0;

output z;

assign #5

z = ({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00000000) ? 0 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b10000000) ? i7 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b01000000) ? i6 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00100000) ? i5 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00010000) ? i4 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00001000) ? i3 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00000100) ? i2 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00000010) ? i1 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00000001) ? i0 :

1'bx;

endmodule

`timescale 1ns/100ps

module mux_8_to_1 (i7, i6, i5, i4, i3, i2, i1, i0,

s7, s6, s5, s4, s3, s2, s1, s0, z );

input i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0;

output z;

wire z = | ({i7, i6, i5, i4, i3, i2, i1, i0} & {s7, s6, s5, s4, s3, s2, s1, s0});

endmodule

`timescale 1ns/100ps

module mux_8_to_1 (i7, i6, i5, i4, i3, i2, i1, i0,

s7, s6, s5, s4, s3, s2, s1, s0, z );

input i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0;

output z;

assign z = | ({i7, i6, i5, i4, i3, i2, i1, i0} & {s7, s6, s5, s4, s3, s2, s1, s0});

endmodule

`timescale 1ns/100ps

module mux_8_to_1 (i7, i6, i5, i4, i3, i2, i1, i0,

s7, s6, s5, s4, s3, s2, s1, s0, z );

input i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0;

output z;

assign z = i7 & s7 | i6 & s6 | i5 & s5 | i4 & s4 | i3 & s3 | i2 & s2 | i1 & s1 | i0 & s0;

endmodule

`timescale 1ns/100ps

module mux_8_to_1 (i7, i6, i5, i4, i3, i2, i1, i0,

s7, s6, s5, s4, s3, s2, s1, s0, z );

input i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0;

output z;

wire #(5,7) z = | ({i7, i6, i5, i4, i3, i2, i1, i0} & {s7, s6, s5, s4, s3, s2, s1, s0});

endmodule

`timescale 1ns/100ps

module mux_8_to_1 (i7, i6, i5, i4, i3, i2, i1, i0,

s7, s6, s5, s4, s3, s2, s1, s0, z );

input i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0;

output z;

assign z = s7 == 1 ? i7 : 1'bz;

assign z = s6 == 1 ? i6 : 1'bz;

assign z = s5 == 1 ? i5 : 1'bz;

assign z = s4 == 1 ? i4 : 1'bz;

assign z = s3 == 1 ? i3 : 1'bz;

assign z = s2 == 1 ? i2 : 1'bz;

assign z = s1 == 1 ? i1 : 1'bz;

assign z = s0 == 1 ? i0 : 1'bz;

endmodule

`timescale 1ns/100ps

module mux_8_to_1 (i7, i6, i5, i4, i3, i2, i1, i0,

s7, s6, s5, s4, s3, s2, s1, s0, z );

input i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0;

output z;

assign z = s7 == 1 ? i7 : 1'bz;

assign z = s6 == 1 ? i6 : 1'bz;

assign z = s5 == 1 ? i5 : 1'bz;

assign z = s4 == 1 ? i4 : 1'bz;

assign z = s3 == 1 ? i3 : 1'bz;

assign z = s2 == 1 ? i2 : 1'bz;

assign z = s1 == 1 ? i1 : 1'bz;

assign z = s0 == 1 ? i0 : 1'bz;

endmodule

`timescale 1ns/100ps

primitive mux_8_to_1 (z, i7, i6, i5, i4, i3, i2, i1, i0,

s7, s6, s5, s4, s3, s2, s1, s0);

input i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0;

output z;

table

// i: 7,6,5,4,3,2,1,0 s: 7,6,5,4,3,2,1,0 z

0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? : 0;

? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 : 0;

1 ? ? ? ? ? ? ? 1 0 0 0 0 0 0 0 : 1;

? 1 ? ? ? ? ? ? 0 1 0 0 0 0 0 0 : 1;

? ? 1 ? ? ? ? ? 0 0 1 0 0 0 0 0 : 1;

? ? ? 1 ? ? ? ? 0 0 0 1 0 0 0 0 : 1;

? ? ? ? 1 ? ? ? 0 0 0 0 1 0 0 0 : 1;

? ? ? ? ? 1 ? ? 0 0 0 0 0 1 0 0 : 1;

? ? ? ? ? ? 1 ? 0 0 0 0 0 0 1 0 : 1;

? ? ? ? ? ? ? 1 0 0 0 0 0 0 0 1 : 1;

0 ? ? ? ? ? ? ? 1 0 0 0 0 0 0 0 : 0;

? 0 ? ? ? ? ? ? 0 1 0 0 0 0 0 0 : 0;

? ? 0 ? ? ? ? ? 0 0 1 0 0 0 0 0 : 0;

? ? ? 0 ? ? ? ? 0 0 0 1 0 0 0 0 : 0;

? ? ? ? 0 ? ? ? 0 0 0 0 1 0 0 0 : 0;

? ? ? ? ? 0 ? ? 0 0 0 0 0 1 0 0 : 0;

? ? ? ? ? ? 0 ? 0 0 0 0 0 0 1 0 : 0;

? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 1 : 0;

endtable

endprimitive

`timescale 1ns/100ps

module mux_8_to_1 (i7, i6, i5, i4, i3, i2, i1, i0,

s7, s6, s5, s4, s3, s2, s1, s0, z );

input i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0;

output z;

assign

z = ({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00000000) ? 0 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b10000000) ? i7 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b01000000) ? i6 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00100000) ? i5 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00010000) ? i4 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00001000) ? i3 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00000100) ? i2 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00000010) ? i1 :

({s7, s6, s5, s4, s3, s2, s1, s0} === 8'b00000001) ? i0 :

1'bx;

endmodule

// Verilog test bench and stimulus for mux_8_to_1

`timescale 10ns/1ns

module test_mux_8_to_1;

wire z;

reg i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0;

mux_8_to_1 u1 (z, i7, i6, i5, i4, i3, i2, i1, i0, s7, s6, s5, s4, s3, s2, s1, s0);

initial

begin

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00000000;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b01000000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b01000000;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b01000000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b01100000;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b01000000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00010000;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b01010000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00010000;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b01000000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00001000;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b00000000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00000100;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b01000100;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00000010;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b00100000;

#50;

{s7, s6, s5, s4, s3, s2, s1, s0} = 8'b00000001;

{i7, i6, i5, i4, i3, i2, i1, i0} = 8'b10000001;

#50;

end

endmodule`timescale 1ns/100ps

module nand2oc (a, b, z);

input a, b;

output z;

parameter tplh = 10, tphl = 12;

assign #(0,tplh,tphl) z = (a & b) == 1 ? 0 : (a & b) == 0 ? 1'bz : 1'bx;

endmodule

// Verilog test bench and stimulus for nand2oc

`timescale 10ns/1ns

module test_nand2oc;

reg a, b;

wire z;

nand2oc u1 (a, b, z);

initial

begin

a = 0; b = 0; #270; $stop;

end

always #50 a = ~a;

always #30 b = ~b;

endmodule

`timescale 1ns/100ps

module sequential_comparator (data, clk, reset, matches);

input [7:0] data;

input clk, reset;

output [3:0] matches;

reg [3:0] matches;

reg [7:0] buff;

always @(negedge clk) buff = data;

always @(negedge clk)

matches = (reset == 1) ? 0 : (data == buff) ? matches + 1 : matches;

endmodule

`timescale 10ns/1ns

module test_sequential_comparator;

reg [7:0] data;

reg clk, reset;

wire [3:0] count;

sequential_comparator u1 (data, clk, reset, count);

initial begin clk = 0; reset = 1; data = 0; #20 reset = 0; #850 $stop; end

initial fork

#020 data = 8'b11110101;

#120 data = 8'b01010110;

#170 data = 8'b11111110;

#320 data = 8'b01010100;

#370 data = 8'b00010001;

#420 data = 8'b10010110;

join

always clk = #50 ~clk;

endmodule

`timescale 1ns/100ps

module sn7403 (a1, a2, a3, a4, b1, b2, b3, b4, y1, y2, y3, y4);

input a1, a2, a3, a4, b1, b2, b3, b4;

output y1, y2, y3, y4;

nand2oc u1 (a1, b1, y1);

nand2oc u2 (a2, b2, y2);

nand2oc u3 (a3, b3, y3);

nand2oc u4 (a4, b4, y4);

endmodule

`timescale 10ns/1ns

module test_xnor;

reg aa, bb;

reg [3:0] i;

initial begin

for (i=0; i<=14; i=i+1) aa <= #(i*30) i[0];

for (i=0; i<=14; i=i+1) bb <= #(i*40) ~i[0];

#200 $stop;

end

sn7403 u1 (

aa, bb, pullup1, pullup2,

aa, bb, bb, aa,

pullup1, pullup2, pullup3, pullup3);

pullup

p1 (pullup1),

p2 (pullup2),

p3 (pullup3);

endmodule

`timescale 1ns/100ps

module y_circuit (a, b, c, d, circuit_node);

input a, b, c, d;

output circuit_node;

assign circuit_node = a;

assign circuit_node = b;

assign circuit_node = c;

assign circuit_node = d;

endmodule

// Verilog test bench and stimulus for de_flipflop

`timescale 10ns/1ns

module test_y_circuit;

reg a, b, c, d;

wire circuit_node;

y_circuit u1 (a, b, c, d, circuit_node);

initial #50 $stop;

always begin a = 1'b0; #10 a = 1'b1; #10 a = 1'bx; #10 a = 1'bz; end

always begin b = 1'bz; #15 b = 1'bx; #10 b = 1'b1; #12 b = 1'b0; end

always begin c = 1'bz; #13 c = 1'bx; #12 c = 1'b0; #14 c = 1'b1; end

always begin d = 1'bx; #16 d = 1'b1; #16 d = 1'b0; #13 d = 1'bz; end

endmodule