// Verilog code for testing array declaration and initialization

`timescale 10ns/1ns

module array_test;

reg [3:0] a, b;

reg [1:0] c, d;

reg [4:1] atable [13:1];

reg [4:1] btable [13:1];

reg amem [13:1];

reg [4:1] areg;

integer i;

initial

begin

//cannot part-select into memory// atable [1:2] = {4'd10, 4'd33};

atable [1] = 4'd10;

amem [1] = 1'b0;

//cannot take value of array amem// amem = 13'b1100110011110;

areg [1] = 1'b0;

areg [2:1] = 2'b10;

areg [2:1] = {1'b0, 1'b1};

areg = 4'b1010;

//cannot take value of array ..// btable = atable;

end

initial

begin

for (i=1; i<=13; i=i+1)

begin

a = atable [i];

#50;

end

end

endmodule

// Verilog code for testing concatenation

`timescale 10ns/1ns

module concat_test;

reg [3:0] a, b;

reg [1:0] c, d;

reg [4:1] atable [13:1], btable [13:1];

reg amem [13:1];

reg [4:1] areg;

integer i;

initial

begin

{amem [1], atable [1]} = 5'd10;

{areg [1], amem [1]} = 2'b10;

{atable [1], atable [3]} = {4'b1011, 4'b1111};

{atable [2], atable [4]} = 8'b10101101;

//cannot take value of array// btable = 52'b0001_0010_0011_0100_0101_0110_0111_1000_1001_1010_1011_1100_1101;

{btable[1], btable[2], btable[3], btable[4], btable[5], btable[6], btable[7], btable[8], btable[9], btable[10], btable[11], btable[12], btable[13]} = 52'b0001_0010_0011_0100_0101_0110_0111_1000_1001_1010_1011_1100_1101;

areg [1] = 1'b0;

areg [2:1] = 2'b10;

areg [2:1] = {1'b0, 1'b1};

areg = 4'b1010;

end

initial

begin

for (i=1; i<=13; i=i+1)

begin

a = atable [i];

b = btable [i];

#50;

end

end

endmodule

`timescale 1ps/100fs

module inv_rc (a, z);

//

input a;

output z;

parameter c_load = 1E-6, rpu = 2000, rpd = 1000;

supply1 vdd;

supply0 gnd;

nmos #(0, c_load * rpd * 3, 0)

g1 (z, gnd, a);

pmos #(c_load * rpu * 3, 0, 0)

g2 (z, vdd, a);

endmodule

// Verilog test bench and stimulus for inv_rc

`timescale 100ns/1ns

module test_inv_rc;

reg a;

wire z;

inv_rc n (a, z);

defparam n.c_load = 66E-3, n.rpu = 25E3, n.rpd = 15E3;

initial

begin

a = 0;

#25 a = 1; #10 a = 0; #11 a = 1; #11 a = 0;

#30 $stop;

end

endmodule