// Verilog test bench and stimulus for bitcomp

`timescale 10ns/1ns

module test_bit_comparator;

reg a, b, gt, eq, lt;

wire a_gt_b, a_eq_b, a_lt_b;

bit_comparator u1 (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

initial

begin

a = 1'b0;

b = 1'b0;

gt = 1'b0; eq = 1'b1; lt = 1'b0;

#20 a = 1; #20 b = 1; #20 a = 0; #20 b = 0;

#100; $finish;

end

endmodule

`timescale 1ns/100ps

module bit_comparator (

a, b, // data inputs

gt, eq, lt, // previous greater than, equal, less than

a_gt_b, // greater

a_eq_b, // equal

a_lt_b); // less than

//

input a, b, gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire im1, im2, im3, im4, im5, im6, im7, im8, im9, im10;

// a_gt_b output

not #(5, 3)

g0 (im1, a),

g1 (im2, b);

nand #(6, 4)

g2 (im3, a, im2),

g3 (im4, a, gt),

g4 (im5, im2, gt);

nand #(7, 5)

g5 (a_gt_b, im3, im4, im5);

// a_eq_b output

nand #(7, 5)

g6 (im6, im1, im2, eq),

g7 (im7, a, b, eq);

nand #(6, 4)

g8 (a_eq_b, im6, im7);

// a_lt_b output

nand #(6, 4)

g9 (im8, im1, b),

g10 (im9, im1, lt),

g11 (im10, b, lt);

nand #(7, 5)

g12 (a_lt_b, im8, im9, im10);

endmodule

`timescale 1ns/100ps

module bit_comparator (

a, b, // data inputs

gt, eq, lt, // previous greater than, equal, less than

a_gt_b, // greater

a_eq_b, // equal

a_lt_b); // less than

//

input a, b, gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire im1, im2, im3, im4, im5, im6, im7, im8, im9, im10;

// a_gt_b output

not #(6:5:4, 4:3:2)

g0 (im1, a),

g1 (im2, b);

nand #(7:6:5, 5:4:3)

g2 (im3, a, im2),

g3 (im4, a, gt),

g4 (im5, im2, gt);

nand #(8:7:6, 6:5:4)

g5 (a_gt_b, im3, im4, im5);

// a_eq_b output

nand #(8:7:6, 6:5:4)

g6 (im6, im1, im2, eq),

g7 (im7, a, b, eq);

nand #(7:6:5, 5:4:3)

g8 (a_eq_b, im6, im7);

// a_lt_b output

nand #(7:6:5, 5:4:3)

g9 (im8, im1, b),

g10 (im9, im1, lt),

g11 (im10, b, lt);

nand #(8:7:6, 6:5:4)

g12 (a_lt_b, im8, im9, im10);

endmodule

`timescale 1ns/100ps

// timed and parameterized

module bit_comparator (

a, b, // data inputs

gt, eq, lt, // previous greater than, equal, less than

a_gt_b, // greater

a_eq_b, // equal

a_lt_b); // less than

//

input a, b, gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

parameter tplh1 = 5, tphl1 = 3,

tplh2 = 6, tphl2 = 4,

tplh3 = 7, tphl3 = 5;

wire im1, im2, im3, im4, im5, im6, im7, im8, im9, im10;

// a_gt_b output

not #(tplh1, tplh1)

g0 (im1, a),

g1 (im2, b);

nand #(tplh2, tplh2)

g2 (im3, a, im2),

g3 (im4, a, gt),

g4 (im5, im2, gt);

nand #(tplh3, tplh3)

g5 (a_gt_b, im3, im4, im5);

// a_eq_b output

nand #(tplh3, tplh3)

g6 (im6, im1, im2, eq),

g7 (im7, a, b, eq);

nand #(tplh2, tplh2)

g8 (a_eq_b, im6, im7);

// a_lt_b output

nand #(tplh2, tplh2)

g9 (im8, im1, b),

g10 (im9, im1, lt),

g11 (im10, b, lt);

nand #(tplh3, tplh3)

g12 (a_lt_b, im8, im9, im10);

endmodule

`timescale 1ns/100ps

module byte_latch (di, c, qo);

input [7:0] di;

input c;

output [7:0] qo;

parameter delval1 = 0, delval2 = 0;

defparam

c7.delval1 = delval1, c7.delval2 = delval2,

c6.delval1 = delval1, c6.delval2 = delval2,

c5.delval1 = delval1, c5.delval2 = delval2,

c4.delval1 = delval1, c4.delval2 = delval2,

c3.delval1 = delval1, c3.delval2 = delval2,

c2.delval1 = delval1, c2.delval2 = delval2,

c1.delval1 = delval1, c1.delval2 = delval2,

c0.delval1 = delval1, c0.delval2 = delval2;

wire dbar;

d_latch c7 (di[7], c, qo[7]);

d_latch c6 (di[6], c, qo[6]);

d_latch c5 (di[5], c, qo[5]);

d_latch c4 (di[4], c, qo[4]);

d_latch c3 (di[3], c, qo[3]);

d_latch c2 (di[2], c, qo[2]);

d_latch c1 (di[1], c, qo[1]);

d_latch c0 (di[0], c, qo[0]);

endmodule

`timescale 1ns/1ps

module byte_latch (di, c, qo);

input [7:0] di;

input c;

output [7:0] qo;

wire dbar;

specify

specparam d2q_r = 4.444;

specparam d2q_f = 3.333;

specparam c2q_r = 2.222;

specparam c2q_f = 1.111;

(di => qo) = (d2q_r, d2q_f);

(c *> qo) = (c2q_r, c2q_f);

endspecify

d_latch c7 (di[7], c, qo[7]);

d_latch c6 (di[6], c, qo[6]);

d_latch c5 (di[5], c, qo[5]);

d_latch c4 (di[4], c, qo[4]);

d_latch c3 (di[3], c, qo[3]);

d_latch c2 (di[2], c, qo[2]);

d_latch c1 (di[1], c, qo[1]);

d_latch c0 (di[0], c, qo[0]);

endmodule

// Verilog test bench and stimulus for byte_latch

`timescale 10ns/1ns

module test_byte_latch;

reg [7:0] di;

reg clk;

wire [7:0] qo;

defparam u1.delval1 = 0.5, u1.delval2 = 0.4;

byte_latch u1 (di, clk, qo);

initial

begin

clk = 1'b0;

#15 di = 8'd0; #20 di = 8'd66; #25 di = 8'd89; #20 di = 8'd76;

#10 $stop;

end

always #10 clk = ~ clk;

endmodule

// Verilog test bench and stimulus for byte_latch

`timescale 10ns/1ns

module test_byte_latch;

reg [7:0] di;

reg clk;

wire [7:0] qo;

byte_latch u1 (di, clk, qo);

initial

begin

clk = 1'b0;

#15 di = 8'd0;

#18 di = 8'b11111111;

#20 di = 8'd66;

#15 di = 8'd89;

#10 di = 8'd55;

#20 di = 8'd76;

#10 $stop;

end

always #10 clk = ~ clk;

endmodule

`timescale 1ns/100ps

module d_latch (d, c, q);

input d, c;

output q;

parameter delval1 = 0, delval2 = 0;

defparam c1.delval = delval1;

wire dbar;

sr_latch c1 (d, dbar, c, q);

not #delval2 c2 (dbar, d);

endmodule

`timescale 1ns/100ps

module d_latch (d, c, q);

input d, c;

output q;

wire dbar;

sr_latch c1 (d, dbar, c, q);

not c2 (dbar, d);

endmodule

`timescale 1ns/100ps

module bit_comparator (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

function fgl;

input w, x, gl;

begin

fgl = w & gl | ~x & gl | w & ~x;

end

endfunction

function feq;

input w, x, eq;

begin

feq = w & x & eq | ~w & ~x & eq ;

end

endfunction

input a, b, gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

assign #12 a_gt_b = fgl (a, b, gt);

assign #12 a_eq_b = feq (a, b, eq);

assign #12 a_lt_b = fgl (b, a, lt);

endmodule

`timescale 1ns/100ps

module bit_comparator (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

function fgl;

input w, x, gl;

begin

fgl = w & gl | ~x & gl | w & ~x;

end

endfunction

function feq;

input w, x, eq;

begin

feq = w & x & eq | ~w & ~x & eq ;

end

endfunction

input a, b, gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

assign a_gt_b = fgl (a, b, gt);

assign a_eq_b = feq (a, b, eq);

assign a_lt_b = fgl (b, a, lt);

endmodule

module nibble_comparator (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

input [3:0] a, b;

input gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire [0:8] im;

bit_comparator c0 (a[0], b[0], gt, eq, lt, im[0], im[1], im[2]);

bit_comparator c1 (a[1], b[1], im[0], im[1], im[2], im[3], im[4], im[5]);

bit_comparator c2 (a[2], b[2], im[3], im[4], im[5], im[6], im[7], im[8]);

bit_comparator c3 (a[3], b[3], im[6], im[7], im[8], a_gt_b, a_eq_b, a_lt_b);

endmodule

// Verilog test bench and stimulus for nibble_comparator

`timescale 10ns/1ns

module test_nibble_comparator;

reg [3:0] a, b;

supply0 gt, lt; supply1 eq;

wire a_gt_b, a_eq_b, a_lt_b;

reg [4:1] atable [13:1], btable [13:1];

integer i;

nibble_comparator u1 (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

initial

begin

$readmemh ("avalues.dat", atable);

$readmemh ("bvalues.dat", btable);

for (i=1; i<=13; i=i+1)

begin

a = atable [i];

b = btable [i];

#50;

end

end

endmodule

// Verilog test bench and stimulus for nibble_comparator

`timescale 10ns/1ns

module test_nibble_comparator;

reg [3:0] a, b;

supply0 gt, lt; supply1 eq;

wire a_gt_b, a_eq_b, a_lt_b;

integer i;

nibble_comparator u1 (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

initial

for (i=1; i<=13; i=i+1)

begin

generate_data (a, b);

#50;

end

//

task generate_data;

output [3:0] target1, target2;

begin : rangen

reg [7:0] values;

values = $random;

target1 = values [7:4];

target2 = values [3:0];

if (target1 == target2)

target2 = ~ target1;

end

endtask

endmodule

// Verilog test bench and stimulus for nibble_comparator

`timescale 10ns/1ns

module test_nibble_comparator;

reg [3:0] a, b;

supply0 gt, lt; supply1 eq;

wire a_gt_b, a_eq_b, a_lt_b;

nibble_comparator u1 (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

initial apply_data (a, "xvalues.dat", 50);

initial apply_data (b, "yvalues.dat", 50);

//

task apply_data;

output [3:0] target;

input [8*11:1] file;

input [8:0] dtime;

integer i;

begin : rr

reg [3:0] values [1:13];

$readmemh (file, values);

for (i=1; i<=13; i=i+1)

begin

target = values [i];

#dtime;

end

end

endtask

endmodule

// Ports defined by name instead of by order

module nibble_comparator (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

input [3:0] a, b;

input gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire [0:8] im;

bit_comparator c0 (.a(a[0]), .b(b[0]), .gt(gt), .eq(eq), .lt(lt),

.a_gt_b(im[0]), .a_eq_b(im[1]), .a_lt_b(im[2]) );

bit_comparator c1 (.a(a[1]), .b(b[1]),

.gt(im[0]), .eq(im[1]), .lt(im[2]),

.a_gt_b(im[3]), .a_eq_b(im[4]), .a_lt_b(im[5]) );

bit_comparator c2 (.a(a[2]), .b(b[2]),

.gt(im[3]), .eq(im[4]), .lt(im[5]),

.a_gt_b(im[6]), .a_eq_b(im[7]), .a_lt_b(im[8]) );

bit_comparator c3 (.a(a[3]), .b(b[3]),

.gt(im[6]), .eq(im[7]), .lt(im[8]),

.a_gt_b(a_gt_b), .a_eq_b(a_eq_b), .a_lt_b(a_lt_b) );

endmodule

`timescale 1ns/1ps

module nibble_comparator (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

input [3:0] a, b;

input gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire [0:8] im;

specify

specparam data2out = 6.666;

specparam control2out = 8.888;

(gt, eq, lt => a_gt_b) = control2out;

(gt, eq, lt => a_eq_b) = control2out;

(gt, eq, lt => a_lt_b) = control2out;

(a, b *> a_gt_b, a_eq_b, a_lt_b) = data2out;

endspecify

bit_comparator c0 (a[0], b[0], gt, eq, lt, im[0], im[1], im[2]);

bit_comparator c1 (a[1], b[1], im[0], im[1], im[2], im[3], im[4], im[5]);

bit_comparator c2 (a[2], b[2], im[3], im[4], im[5], im[6], im[7], im[8]);

bit_comparator c3 (a[3], b[3], im[6], im[7], im[8], a_gt_b, a_eq_b, a_lt_b);

endmodule

// Verilog test bench and stimulus for nibble_comparator

`timescale 10ns/1ns

module test_nibble_comparator;

reg [3:0] a, b;

reg gt, lt, eq;

wire a_gt_b, a_eq_b, a_lt_b;

reg [4:1] atable [13:1], btable [13:1];

integer i;

nibble_comparator u1 (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

initial

begin

$readmemh ("avalues.dat", atable);

$readmemh ("bvalues.dat", btable);

for (i=1; i<=13; i=i+1)

begin

a = atable [i];

b = btable [i];

#50;

end

end

initial

begin

{gt, eq, lt} = {1'b0, 1'b1, 1'b0};

#470;

{gt, eq, lt} = 3'b100;

#10;

{gt, eq, lt} = 3'b011;

end

endmodule

module nibble_comparator (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

input [3:0] a, b;

input gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire [0:8] im;

bit_comparator c0 (a[0], b[0], gt, eq, lt, im[0], im[1], im[2]);

bit_comparator c1 (a[1], b[1], im[0], im[1], im[2], im[3], im[4], im[5]);

bit_comparator c2 (a[2], b[2], im[3], im[4], im[5], im[6], im[7], im[8]);

bit_comparator c3 (a[3], b[3], im[6], im[7], im[8], a_gt_b, a_eq_b, a_lt_b);

endmodule

module timed_nibble_comparator;

defparam

nibble_comparator.c0.tplh1 = 20,

nibble_comparator.c1.tplh1 = 20,

nibble_comparator.c2.tplh1 = 20,

nibble_comparator.c3.tplh1 = 20;

endmodule

// Passing parameters one level down

module nibble_comparator (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

input [3:0] a, b;

input gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire [0:8] im;

defparam c0.tplh1 = 20, c1.tplh1 = 20, c2.tplh1 = 20, c3.tplh1 = 20;

bit_comparator c0 (a[0], b[0], gt, eq, lt, im[0], im[1], im[2]);

bit_comparator c1 (a[1], b[1], im[0], im[1], im[2], im[3], im[4], im[5]);

bit_comparator c2 (a[2], b[2], im[3], im[4], im[5], im[6], im[7], im[8]);

bit_comparator c3 (a[3], b[3], im[6], im[7], im[8], a_gt_b, a_eq_b, a_lt_b);

endmodule

// Passing parameters two levels down

module passed_nibble_comparator (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

input [3:0] a, b;

input gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire [0:8] im;

parameter delval = 1;

defparam

c0.tplh1 = delval, c1.tplh1 = delval, c2.tplh1 = delval, c3.tplh1 = delval,

c0.tplh2 = delval, c1.tplh2 = delval, c2.tplh2 = delval, c3.tplh2 = delval,

c0.tplh3 = delval, c1.tplh3 = delval, c2.tplh3 = delval, c3.tplh3 = delval,

c0.tphl1 = delval, c1.tphl1 = delval, c2.tphl1 = delval, c3.tphl1 = delval,

c0.tphl2 = delval, c1.tphl2 = delval, c2.tphl2 = delval, c3.tphl2 = delval,

c0.tphl3 = delval, c1.tphl3 = delval, c2.tphl3 = delval, c3.tphl3 = delval;

bit_comparator c0 (a[0], b[0], gt, eq, lt, im[0], im[1], im[2]);

bit_comparator c1 (a[1], b[1], im[0], im[1], im[2], im[3], im[4], im[5]);

bit_comparator c2 (a[2], b[2], im[3], im[4], im[5], im[6], im[7], im[8]);

bit_comparator c3 (a[3], b[3], im[6], im[7], im[8], a_gt_b, a_eq_b, a_lt_b);

endmodule

// Verilog test bench and stimulus for nibble_comparator

// Passing parameters two levels down

`timescale 10ns/1ns

module test_nibble_comparator;

reg [3:0] a, b;

supply0 gt, lt; supply1 eq;

wire a_gt_b, a_eq_b, a_lt_b;

reg [4:1] atable [13:1], btable [13:1];

defparam u1.delval = 20;

integer i;

passed_nibble_comparator u1 (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

initial

begin

$readmemh ("avalues.dat", atable);

$readmemh ("bvalues.dat", btable);

for (i=1; i<=13; i=i+1)

begin

a = atable [i];

b = btable [i];

#50;

end

end

endmodule

`timescale 1ns/100ps

module parity (a, odd, even);

input [7:0] a;

output odd, even;

parameter delval1 = 0.0, delval2 = 0.0;

wire [5:0] im;

xor #(delval1) x0 (odd, im[5], a[7]);

xor #(delval1) x[1:5] (im[5:1], im[4:0], a[6:2]);

xor #(delval2) x6 (im[0], a[0], a[1]);

assign even = ~ odd;

endmodule

// Verilog test bench and stimulus for parity

`timescale 10ns/1ns

module test_parity;

reg [7:0] xi;

wire odd, even;

parity u1 (xi, odd, even);

defparam u1.delval1 = 0.5, u1.delval2 = 1.0;

initial

begin

#15 xi = 8'h0; #20 xi = 8'hAB;

#25 xi = 8'h47; #20 xi = 8'hB6;

#10 $stop;

end

endmodule

`timescale 1ns/100ps

module sr_latch (s, r, c, q);

//

input s, r, c;

output q;

parameter delval = 0;

wire im1, im2, im3;

nand #(delval)

g1 (im1, s, c),

g2 (im2, r, c),

g3 (q, im1, im3),

g4 (im3, q, im2);

endmodule

`timescale 1ns/100ps

module sr_latch (s, r, c, q);

//

input s, r, c;

output q;

wire im1, im2, im3;

nand

g1 (im1, s, c),

g2 (im2, r, c),

g3 (q, im1, im3),

g4 (im3, q, im2);

endmodule

module top;

reg clk;

reg [0:4] in1;

reg [0:9] in2;

wire [0:4] o1;

wire [0:9] o2;

vdff m1 (o1, in1, clk);

vdff m2 (o2, in2, clk);

endmodule

module vdff (out, in, clk);

parameter size = 1, delay = 1;

input [0:size-1] in;

input clk;

output [0:size-1] out;

reg [0:size-1] out;

always @(posedge clk)

#delay out = in;

endmodule

module annotate;

defparam

top.m1.size = 5,

top.m1.delay = 10,

top.m2.size = 10,

top.m2.delay = 20;

endmodule

`