module nibble_comparator (

a, b, // data inputs

gt, eq, lt, // previous greater than, equal, less than

a_gt_b, // greater

a_eq_b, // equal

a_lt_b); // less than

//

input [3:0] a, b;

input gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire [0:8] im;

bit_comparator cc[0:3] ( a, b,

{im[6],im[3],im[0],gt}, {im[7],im[4],im[1],eq}, {im[8],im[5],im[2],lt},

{a_gt_b,im[6],im[3],im[0]}, {a_eq_b,im[7],im[4],im[1]}, {a_lt_b,im[8],im[5],im[2]});

/*

bit_comparator c0 (a[0], b[0], gt, eq, lt, im[0], im[1], im[2]);

bit_comparator c1 (a[1], b[1], im[0], im[1], im[2], im[3], im[4], im[5]);

bit_comparator c2 (a[2], b[2], im[3], im[4], im[5], im[6], im[7], im[8]);

bit_comparator c3 (a[3], b[3], im[6], im[7], im[8], a_gt_b, a_eq_b, a_lt_b);

*/

endmodule

`timescale 10ns/1ns

//

module test_xor8;

reg [1:8] xin1, xin2;

wire [1:8] xout;

xor8 u1 (xout, xin1, xin2);

initial

begin

xin1 = 1'd0; xin2 = 1'd0;

#50 xin1 = 1'd15; xin2 = 1'd14;

#50 ;

#50 xin1 = 1'd14; xin2 = 1'd15;

#50 ;

#50 xin1 = 1'd12;

#50 ;

#50 xin1 = 1'd10;

#50 $finish;

end

endmodule

//

module xor8(xout, xin1, xin2);

output [1:8] xout;

input [1:8] xin1, xin2;

xor a[1:8] (xout, xin1, xin2);

endmodule `timescale 10ns/1ns

//

module test_xor8;

reg [1:8] xin1, xin2;

wire [1:8] xout;

xor8 u1 (xout, xin1, xin2);

initial

begin

xin1 = 1'd0; xin2 = 1'd0;

#50 xin1 = 8'd15; xin2 = 8'd14;

#50 ;

#50 xin1 = 8'd14; xin2 = 8'd15;

#50 ;

#50 xin1 = 8'd12;

#50 ;

#50 xin1 = 8'd10;

#50 $finish;

end

endmodule

//

module xor1 (xout, xin1, xin2);

output xout;

input xin1, xin2;

assign xout = xin1 & xin2;

endmodule

//

module xor8(xout, xin1, xin2);

output [1:8] xout;

input [1:8] xin1, xin2;

xor1 a (xout, xin1, xin2);

endmodule

`timescale 10ns/1ns

//

module test_driver;

reg [3:0] in;

reg en;

wire [3:0] out;

driver u1(out, in, en);

initial

begin

in = 1'd0; en = 1;

#50 in = 4'd15; en = 0;

#50 ;

#50 in = 4'd14; en = 1;

#50 ;

#50 in = 4'd12;

#50 ;

#50 in = 4'd10;

#50 $finish;

end

endmodule

//

module driver (in, out, en);

output [3:0] out;

input [3:0] in;

input en;

bufif0 ar[3:0] (out, in, {en, en, en, en});

endmodule

`timescale 1ns/100ps

module bit_comparator (

a, b, // data inputs

gt, eq, lt, // previous greater than, equal, less than

a_gt_b, // greater

a_eq_b, // equal

a_lt_b); // less than

//

input a, b, gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire im1, im2, im3, im4, im5, im6, im7, im8, im9, im10;

// a_gt_b output

not #(4)

g0 (im1, a),

g1 (im2, b);

nand #(5)

g2 (im3, a, im2),

g3 (im4, a, gt),

g4 (im5, im2, gt);

nand #(6)

g5 (a_gt_b, im3, im4, im5);

// a_eq_b output

nand #(6)

g6 (im6, im1, im2, eq),

g7 (im7, a, b, eq);

nand #(5)

g8 (a_eq_b, im6, im7);

// a_lt_b output

nand #(5)

g9 (im8, im1, b),

g10 (im9, im1, lt),

g11 (im10, b, lt);

nand #(6)

g12 (a_lt_b, im8, im9, im10);

endmodule

`timescale 1ns/100ps

module bit_comparator (

a, b, // data inputs

gt, eq, lt, // previous greater than, equal, less than

a_gt_b, // greater

a_eq_b, // equal

a_lt_b); // less than

//

input a, b, gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wand im345, im67, im890;

wire im1, im2;

// a_gt_b output

not #(4)

g0 (im1, a),

g1 (im2, b);

nand (highz1, strong0) #(5)

g2 (im345, a, im2),

g3 (im345, a, gt),

g4 (im345, im2, gt);

not #6 (a_gt_b, im345);

// a_eq_b output

nand (highz1, strong0) #(6)

g6 (im67, im1, im2, eq),

g7 (im67, a, b, eq);

not #5 (a_eq_b, im67);

// a_lt_b output

nand (highz1, strong0) #(5)

g9 (im890, im1, b),

g10 (im890, im1, lt),

g11 (im890, b, lt);

not #6 (a_lt_b, im890);

endmodule

`timescale 1ns/100ps

module bit_comparator (

a, b, // data inputs

gt, eq, lt, // previous greater than, equal, less than

a_gt_b, // greater

a_eq_b, // equal

a_lt_b); // less than

//

input a, b, gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wand im345, im67, im890;

wire im1, im2;

pullup (pull1)

p1 (im345),

p2 (im67),

p3 (im890);

// a_gt_b output

not #(4)

g0 (im1, a),

g1 (im2, b);

nand (highz1, strong0) #(5)

g2 (im345, a, im2),

g3 (im345, a, gt),

g4 (im345, im2, gt);

not #6 (a_gt_b, im345);

// a_eq_b output

nand (highz1, strong0) #(6)

g6 (im67, im1, im2, eq),

g7 (im67, a, b, eq);

not #5 (a_eq_b, im67);

// a_lt_b output

nand (highz1, strong0) #(5)

g9 (im890, im1, b),

g10 (im890, im1, lt),

g11 (im890, b, lt);

not #6 (a_lt_b, im890);

endmodule

`timescale 1ns/100ps

module bit_comparator (

a, b, // data inputs

gt, eq, lt, // previous greater than, equal, less than

a_gt_b, // greater

a_eq_b, // equal

a_lt_b); // less than

//

input a, b, gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire im1, im2;

wor im345, im67, im890;

pulldown (pull0)

p1 (im345),

p2 (im67),

p3 (im890);

// a_gt_b output

not #(4)

g0 (im1, a),

g1 (im2, b);

and (highz0, strong1) #(5)

g2 (im345, a, im2),

g3 (im345, a, gt),

g4 (im345, im2, gt);

assign #6 a_gt_b = im345;

// a_eq_b output

and (highz0, strong1) #(6)

g6 (im67, im1, im2, eq),

g7 (im67, a, b, eq);

assign #5 a_eq_b = im67;

// a_lt_b output

and (highz0, strong1) #(5)

g9 (im890, im1, b),

g10 (im890, im1, lt),

g11 (im890, b, lt);

assign #6 a_lt_b = im890;

endmodule

`timescale 1ns/100ps

module bit_comparator (

a, b, // data inputs

gt, eq, lt, // previous greater than, equal, less than

a_gt_b, // greater

a_eq_b, // equal

a_lt_b); // less than

// Cannot specify delay values on wired logic.

input a, b, gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire im1, im2;

wor a_gt_b, a_eq_b, a_lt_b;

pulldown (a_gt_b), (a_eq_b), (a_lt_b);

// a_gt_b output

not #(4)

g0 (im1, a),

g1 (im2, b);

and (highz0, strong1) #(5)

g2 (a_gt_b, a, im2),

g3 (a_gt_b, a, gt),

g4 (a_gt_b, im2, gt);

// a_eq_b output

and (highz0, strong1) #(6)

g6 (a_eq_b, im1, im2, eq),

g7 (a_eq_b, a, b, eq);

// a_lt_b output

and (highz0, strong1) #(5)

g9 (a_lt_b, im1, b),

g10 (a_lt_b, im1, lt),

g11 (a_lt_b, b, lt);

endmodule

// Verilog test bench and stimulus for bitcomp

`timescale 10ns/1ns

module test_bit_comparator;

reg a, b, gt, eq, lt;

wire a_gt_b, a_eq_b, a_lt_b;

bit_comparator u1 (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

initial

begin

a = 1'b0;

b = 1'b0;

gt = 1'b0; eq = 1'b1; lt = 1'b0;

#20 a = 1; #20 b = 1; #20 a = 0; #20 b = 0;

#100; $finish;

end

endmodule

`timescale 1ns/100ps

module byte_latch (di, c, qo);

input [7:0] di;

input c;

output [7:0] qo;

wire dbar;

d_latch c7 (di[7], c, qo[7]);

d_latch c6 (di[6], c, qo[6]);

d_latch c5 (di[5], c, qo[5]);

d_latch c4 (di[4], c, qo[4]);

d_latch c3 (di[3], c, qo[3]);

d_latch c2 (di[2], c, qo[2]);

d_latch c1 (di[1], c, qo[1]);

d_latch c0 (di[0], c, qo[0]);

endmodule

module byte_comparator (

a, b, // data inputs

gt, eq, lt, // previous greater than, equal, less than

a_gt_b, // greater

a_eq_b, // equal

a_lt_b); // less than

//

input [7:0] a, b;

input gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire [0:20] im;

bit_comparator c0 (a[0], b[0], gt, eq, lt, im[0], im[1], im[2]);

bit_comparator c1 (a[1], b[1], im[00], im[01], im[02], im[03], im[04], im[05]);

bit_comparator c2 (a[2], b[2], im[03], im[04], im[05], im[06], im[07], im[08]);

bit_comparator c3 (a[3], b[3], im[06], im[07], im[08], im[09], im[10], im[11]);

bit_comparator c4 (a[4], b[4], im[09], im[10], im[11], im[12], im[13], im[14]);

bit_comparator c5 (a[5], b[5], im[12], im[13], im[14], im[15], im[16], im[17]);

bit_comparator c6 (a[6], b[6], im[15], im[16], im[17], im[18], im[19], im[20]);

bit_comparator c7 (a[7], b[7], im[18], im[19], im[20], a_gt_b, a_eq_b, a_lt_b);

endmodule

`timescale 1ns/100ps

module byte_latch (di, clk, qo);

//

input [7:0] di;

input clk;

output [7:0] qo;

sr_latch sr[7:0] (di, r, c, q);

endmodule

// Verilog test bench and stimulus for byte_latch

`timescale 10ns/1ns

module test_byte_latch;

reg [7:0] di;

reg clk;

wire [7:0] qo;

byte_latch u1 (di, clk, qo);

initial

begin

clk = 1'b0;

#10 di = 8'd0; #10 di = 8'd66; #10 di = 8'd89;

#10 $finish;

end

always #10 clk = ~ clk;

endmodule

`timescale 1ns/100ps

module cmos_nand (a, b, z);

//

input a, b;

output z;

supply1 vdd;

supply0 gnd;

wire im1;

nmos #(4)

g1 (z, im1, a),

g2 (im1, gnd, b);

pmos #(5)

g4 (z, vdd, a),

g5 (z, vdd, b);

endmodule

// Verilog test bench and stimulus for cmos_nand

`timescale 100ns/1ns

module test_cmos_nand;

reg a, b;

wire z;

cmos_nand n (a, b, z);

initial

begin

a = 0; b = 1;

#25 a = 1; #11 b = 0;

#10 a = 0; #10 b = 1;

#11 a = 1; #11 b = 0;

#30 $stop;

end

endmodule

`timescale 1ns/100ps

module cmos_sr_latch (s, r, c, q);

//

input s, r, c;

output q;

wire im1, im2, im3;

cmos_nand

g1 (s, c, im1),

g3 (im1, im3, q);

cmos_nand

g2 (r, c, im2),

g4 (q, im2, im3);

endmodule

// Verilog test bench and stimulus for sr_latch

`timescale 10ns/1ns

module test_cmos_sr_latch;

reg s, r, c;

wire q;

cmos_sr_latch u1 (s, r, c, q);

initial

begin

s = 0; r = 0; c = 1;

#25 s = 1; #11 s = 0;

#10 r = 1; #10 r = 0;

#11 s = 1; #11 s = 0;

#30 $finish;

end

always #10 c = ~ c;

endmodule

`timescale 1ns/100ps

module dd_latch (d, c, q);

//

input d, c;

output q;

wire im1, cnot, qnot;

not #(5)

g1 (cnot, c),

g2 (qnot, im1),

g3 (q, qnot);

cmos #(3)

g4 (im1, d, c, cnot),

g5 (im1, q, cnot, c);

endmodule

// Verilog test bench and stimulus for dd_latch

`timescale 10ns/1ns

module test_dd_latch;

reg d, c;

wire q;

dd_latch u1 (d, c, q);

initial

begin

d = 0; c = 1;

#25 d = 1; #11 d = 0;

#10 d = 1; #10 d = 0;

#11 d = 1; #11 d = 0;

#30 $stop;

end

always #10 c = ~ c;

endmodule

`timescale 1ns/100ps

module dd_master_slave (d, c, q);

//

input d, c;

output q;

wire m, cnot;

trireg #(0, 0, 96) cap1, cap2;

not #(5)

g1 (cnot, c),

g2 (m, cap1),

g3 (q, cap2);

cmos #(3)

g4 (cap1, d, c, cnot),

g5 (cap2, m, cnot, c);

endmodule

// Verilog test bench and stimulus for dd_master_slave

`timescale 10ns/1ns

module test_dd_master_slave;

reg d, c;

wire q;

dd_master_slave u1 (d, c, q);

initial

begin

d = 0; c = 1;

#25 d = 1; #11 d = 0;

#31 d = 1; #11 d = 0;

#30 $finish;

end

always #10 c = ~ c;

endmodule

`timescale 1ns/100ps

module d_latch (d, c, q);

input d, c;

output q;

wire dbar;

sr_latch c1 (d, dbar, c, q);

not #4 c2 (dbar, d);

endmodule

// Verilog test bench and stimulus for d_latch

`timescale 10ns/1ns

module test_d_latch;

reg d, c;

wire q;

d_latch u1 (d, c, q);

initial

begin

d = 0; c = 1;

#25 d = 1; #11 d = 0;

#10 d = 1; #10 d = 0;

#11 d = 1; #11 d = 0;

#30 $stop;

end

always #10 c = ~ c;

endmodule

module nibble_comparator (

a, b, // data inputs

gt, eq, lt, // previous greater than, equal, less than

a_gt_b, // greater

a_eq_b, // equal

a_lt_b); // less than

//

input [3:0] a, b;

input gt, eq, lt;

output a_gt_b, a_eq_b, a_lt_b;

wire [0:8] im;

bit_comparator c0 (a[0], b[0], gt, eq, lt, im[0], im[1], im[2]);

bit_comparator c1 (a[1], b[1], im[0], im[1], im[2], im[3], im[4], im[5]);

bit_comparator c2 (a[2], b[2], im[3], im[4], im[5], im[6], im[7], im[8]);

bit_comparator c3 (a[3], b[3], im[6], im[7], im[8], a_gt_b, a_eq_b, a_lt_b);

endmodule

// Verilog test bench and stimulus for nibble_comparator

`timescale 10ns/1ns

module test_nibble_comparator;

reg [3:0] a, b;

supply0 gt, lt; supply1 eq;

wire a_gt_b, a_eq_b, a_lt_b;

nibble_comparator u1 (a, b, gt, eq, lt, a_gt_b, a_eq_b, a_lt_b);

initial

begin

a = 4'd0; b = 4'd0;

#50 a = 4'd15; b = 4'd14;

#50 ;

#50 a = 4'd14; b = 4'd15;

#50 ;

#50 b = 4'd12;

#50 ;

#50 a = 4'd10;

#50 a = 4'd00; b = 4'd15;

#50 a = 4'd15;

#50 a = 4'd00;

#50 b = 4'd00;

#50 a = 4'd15;

#50 $finish;

end

endmodule

module old_new_comparator (i, clk, gt_compare, eq_compare);

//

input [7:0] i;

input clk;

output gt_compare, eq_compare;

wire [7:0] con1;

supply1 vdd;

supply0 gnd;

byte_latch l (i, clk, con1);

byte_comparator c (con1, i, gnd, vdd, gnd, gt_compare, eq_compare, );

endmodule

// Verilog test bench and stimulus for old_new_comparator

`timescale 100ns/1ns

module test_old_new_comparator;

reg [7:0] i;

reg clk;

wire gt_compare, eq_compare;

old_new_comparator u1 (i, clk, gt_compare, eq_compare);

initial

begin

clk = 1'b0;

#18 i = 8'd0; #18 i = 8'd66; #18 i = 8'd89;

#18 i = 8'd6; #18 i = 8'd73; #18 i = 8'd14;

#18 i = 8'd5; #18 i = 8'd12; #18 i = 8'd76;

#18 $finish;

end

always #10 clk = ~ clk;

endmodule

`timescale 1ns/100ps

module sr_latch (s, r, c, q);

//

input s, r, c;

output q;

wire im1, im2, im3;

nand #(5)

g1 (im1, s, c),

g2 (im2, r, c),

g3 (q, im1, im3),

g4 (im3, q, im2);

endmodule

`timescale 1ns/100ps

module sr_latch (s, r, c, q);

//

input s, r, c;

output q;

wire im1, im2, im3;

nand #(5)

g1 (im1, s, c),

g3 (q, im1, im3);

nand #(3)

g2 (im2, r, c),

g4 (im3, q, im2);

endmodule

// Verilog test bench and stimulus for sr_latch

`timescale 10ns/1ns

module test_sr_latch;

reg s, r, c;

wire q;

sr_latch u1 (s, r, c, q);

initial

begin

s = 0; r = 0; c = 1;

#25 s = 1; #11 s = 0;

#10 r = 1; #10 r = 0;

#11 s = 1; #11 s = 0;

#30 $finish;

end

always #10 c = ~ c;

endmodule