FIGURE 4.1
Value transfer through wires.
FIGURE 4.2
Describing sub-components.
FIGURE 4.3
A VHDL concurrent body.
FIGURE 4.4
A VHDL sequential body.
FIGURE 4.5
A gate circuit to illustrate timing and concurrency.
FIGURE 4.6
Gates of Figure 4.5 reacting to changes originated by a changing from ‘1’ to ‘0’.
FIGURE 4.7
Timing diagram resulting from input a of circuit of Figure 4.5 changing from ‘1’ to ‘0’ at time zero.
FIGURE 4.8
Objects and classes in sequential and concurrent bodies.
|
Using Objects In VHDL |
B O D Y |
|||||||
|
Concurrent |
Sequential |
|||||||
|
Declare |
Assign to |
Use |
Declare |
Assign to |
Use |
|||
|
O B J E |
Signal |
YES |
YES |
YES |
NO |
YES |
YES |
|
|
Variable |
NO |
NO |
YES |
YES |
YES |
YES |
||
|
Constant |
YES |
-- |
YES |
YES |
-- |
YES |
||
|
File |
YES |
-- |
YES |
YES |
-- |
YES |
||
FIGURE 4.9
Objects in VHDL bodies.
ENTITY example IS END ENTITY;
--
ARCHITECTURE delay OF example IS
SIGNAL waveform : BIT;
SIGNAL target1, target2, target3 : BIT;
SIGNAL diff12, diff13, diff23 : BIT;
-- This is a comment
BEGIN
-- Illustrating inertial delay
target1 <= waveform AFTER 5 NS;
target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS;
-- Illustrating transport delay
target3 <= TRANSPORT waveform AFTER 5 NS;
-- Comparing targets
diff12 <= target1 XOR target2;
diff13 <= target1 XOR target3;
diff23 <= target2 XOR target3;
-- Creating waveform
waveform <=
‘1’ AFTER 03 NS, ‘0’ AFTER 08 NS, ‘1’ AFTER 14 NS, ‘0’ AFTER 18 NS,
‘1’ AFTER 24 NS, ‘0’ AFTER 27 NS, ‘1’ AFTER 33 NS, ‘0’ AFTER 35 NS,
‘1’ AFTER 41 NS, ‘0’ AFTER 47 NS, ‘1’ AFTER 52 NS, ‘0’ AFTER 58 NS,
‘1’ AFTER 62 NS, ‘0’ AFTER 68 NS, ‘1’ AFTER 71 NS, ‘0’ AFTER 77 NS,
‘1’ AFTER 79 NS, ‘0’ AFTER 85 NS,
END delay;
FIGURE 4.10
VHDL description for the demonstration of delay mechanisms.
FIGURE 4.11
The RC delay is best represented by inertial delay mechanism.
FIGURE 4.12
Illustrating differences between delay mechanism in VHDL.
ENTITY figure_5_example IS
PORT (a, b, c : IN BIT; z : OUT BIT);
END figure_5_example;
ARCHITECTURE concurrent OF figure_5_example IS
SIGNAL w, x, y : BIT;
BEGIN
w <= NOT a AFTER 12 NS;
x <= a AND b AFTER 12 NS;
y <= c AND w AFTER 12 NS;
z <= x OR y AFTER 12 NS;
END concurrent;
FIGURE 4.13
VHDL description for the gate level circuit in Figure 4.5 for the demonstration of timing and concurrency.
FIGURE 4.14
Resolving a single value from multiple driving values.
FIGURE 4.15
A transaction, from being created to being expired.
ARCHITECTURE demo OF example IS
SIGNAL a, b, c : BIT := '0';
BEGIN
a <= '1' AFTER 15 NS;
b <= NOT a AFTER 5 NS;
c <= a AFTER 10 NS;
END demo;
FIGURE 4.16
A simple description for illustrating events and transactions.
FIGURE 4.17
Events and transaction that occur on signals in Figure 4.16, (a) The resulting timing diagram showing transactions when they become current, (b) Transactions when they are placed on signals, (c) Transactions as their time values approach zero to become current, (d) Transactions from creation to expiration.
ENTITY timing IS
PORT (a, b : IN BIT; z, zbar : BUFFER BIT);
END ENTITY;
--
ARCHITECTURE delta of timing IS
BEGIN
z_bar <= NOT z;
z <= a AND b AFTER 10 NS;
END delta;
FIGURE 4.18
Demonstrating need for delta delay.
ARCHITECTURE not_properly_timed OF figure_5_example IS
SIGNAL w, x, y : BIT := '0';
BEGIN
y <= c AND w;
w <= NOT a;
x <= a AND b;
z <= x OR y AFTER 36 NS;
END not_properly_timed;
FIGURE 4.19
VHDL description for demonstrating the delta delay.
FIGURE 4.20
Timing diagram for the description of Figure 4.19, showing delta delays.
ARCHITECTURE concurrent OF timing_demo IS
SIGNAL a, b, c : BIT := '0';
BEGIN
a <= '1';
b <= NOT a;
c <= NOT b;
END concurrent;
FIGURE 4.21
Description for a chain of two inverters, demonstrating Delta, transactions and concurrency.
FIGURE 4.22
Timing diagram for timing_demo description of Figure 4.21.
(a)
ARCHITECTURE forever OF oscillating IS
SIGNAL x: BIT := ‘0’;
SIGNAL y: BIT := ‘1’;
BEGIN
x <= y;
y <= NOT x;
END forever
(b)
(c)
FIGURE 4.23
Oscillation in zero real time, (a) Circuit to model, (b) VHDL representation, (c) Signal waveforms.
ARCHITECTURE sequential OF sequential_placement IS
. . .
BEGIN
PROCESS
x<= v1 AFTER t1;
x<= v2 AFTER t2;
WAIT;
END PROCESS;
END sequential;
FIGURE 4.24
Sequential placement of transactions in a sequential body of VHDL.
ARCHITECTURE concurrent OF sequential_placement IS
. . .
BEGIN
a <= v1, v2 AFTER t2-t1
x <= a AFTER t2;
END concurrent;
FIGURE 4.25
Sequential placement of transaction in a concurrent body of VHDL.
FIGURE 4.26
Projected output waqveform.
FIGURE 4.27
Multiple drivers of a resolved signal.
FIGURE 4.28
Effective transactions on the driver of a signal when multiple transactions are sequentially placed on the signal driver.
ARCHITECTURE sequential OF discarding_old IS
SIGNAL x : rit := ‘Z’;
BEGIN
PROCESS
BEGIN
x <= ‘1’ AFTER 5 NS;
x <= TRANSPORT ‘0’ AFTER 3 NS;
WAIT;
END PROCESS;
END sequential;
FIGURE 4.29
Discarding previous transactions. The new transaction is scheduled before the existing one.
ARCHITECTURE sequential OF saving_all IS
SIGNAL x : rit := ‘Z’;
BEGIN
PROCESS
BEGIN
x <= ‘1’ AFTER 5 NS;
x <= TRANSPORT ‘0’ AFTER 8 NS;
WAIT;
END PROCESS;
END sequential;
FIGURE 4.30
Appending transactions. Delay type is transport, and the new transaction is after the existing one.
ARCHITECTURE sequential OF overwriting_old IS
SIGNAL x : rit := ‘Z’;
BEGIN
PROCESS
BEGIN
x <= ‘1’ AFTER 5 NS;
x <= ‘0’ AFTER 3 NS;
WAIT;
END PROCESS;
END sequential;
FIGURE 4.31
Discarding previous transactions. The new transactions is scheduled before the existing one.
ARCHITECTURE sequential OF saving_all IS
SIGNAL x : rit := ‘Z’;
BEGIN
PROCESS
BEGIN
x <= ‘0’ AFTER 5 NS;
x <= ‘0’ AFTER 8 NS;
WAIT;
END PROCESS;
END sequential;
FIGURE 4.32
Saving previous transactions of same value. Transactions with the same value are both kept on the driver of x.
ARCHITECTURE sequential OF appending IS
SIGNAL x : rit :=’Z’;
BEGIN
PROCESS
BEGIN
x <= ‘1’ AFTER 5 NS;
x <= REJECT 2 NS INERTIAL ’0’ AFTER 8 NS;
WAIT;
END PROCESS;
END sequential;
FIGURE 4.33
Appending the new transaction of different value. Time difference of new and existing is greater than reject value.
ARCHITECTURE sequential OF discarding_old IS
SIGNAL x : rit :=’Z’;
BEGIN
PROCESS
BEGIN
x <= ‘1’ AFTER 5 NS;
x <= REJECT 4 NS INERTIAL ’0’ AFTER 8 NS;
WAIT;
END PROCESS;
END sequential
FIGURE 4.34
Discarding previous transactions of different value. The new transaction is scheduled after the existing, and has a different value.
ENTITY example IS END ENTITY;
--
ARCHITECTURE delay OF example IS
SIGNAL waveform : BIT;
SIGNAL target1, target2, target3 : BIT;
BEGIN
-- Signal assignments
target1 <= waveform AFTER 5 NS;
target2 <= REJECT 3 NS INERTIAL waveform AFTER 5 NS;
target3 <= TRANSPORT waveform AFTER 5 NS;
-- Creating waveform
waveform <=
'1' AFTER 03 NS, '0' AFTER 08 NS, '1' AFTER 14 NS, '0' AFTER 18 NS,
'1' AFTER 24 NS, '0' AFTER 27 NS, '1' AFTER 33 NS, '0' AFTER 35 NS;
END delay;
FIGURE 4.35
Pulse rejection in inertial, reject, and transport delay.
FIGURE 4.36
New, pending, and expired transactions on targets of Figure 4.35.
ENTITY example IS END ENTITY;
--
ARCHITECTURE delay OF example IS
SIGNAL a, b : BIT;
BEGIN
-- Signal assignments
a <= '1' AFTER 5 NS, '0' AFTER 10 NS, '1' AFTER 15 NS;
b <= '0', a AFTER 3 NS;
END delay;
FIGURE 4.37
Sequential placement of transactions by executing concurrent signal assignments.