ARCHITECTURE functional OF bit_comparator IS
FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS
BEGIN
RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x);
END fgl;
FUNCTION feq (w, x, eq : BIT) RETURN BIT IS
BEGIN
RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq);
END feq;
BEGIN
a_gt_b <= fgl (a, b, gt) AFTER 12 NS;
a_eq_b <= feq (a, b, eq) AFTER 12 NS;
a_lt_b <= fgl (b, a, lt) AFTER 12 NS;
END functional;
FIGURE 6. 1
A functional bit_comparator, using the same function for two outputs.
FIGURE 6. 2
Syntax details of a subprogram body, a general view.
ARCHITECTURE structural OF nibble_comparator IS
COMPONENT comp1
PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
FOR ALL : comp1 USE ENTITY WORK.bit_comparator (functional);
CONSTANT n : INTEGER := 4;
SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1);
BEGIN
c_all: FOR i IN 0 TO n-1 GENERATE
l: IF i = 0 GENERATE
least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) );
END GENERATE;
m: IF i = n-1 GENERATE
most: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1),
a_gt_b, a_eq_b, a_lt_b);
END GENERATE;
r: IF i > 0 AND i < n-1 GENERATE
rest: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1),
im(i*3+0), im(i*3+1), im(i*3+2) );
END GENERATE;
END GENERATE;
END structural;
FIGURE 6. 3
Structural architecture of a nibble_comparator.
ARCHITECTURE procedural OF nibble_comparator_test_bench IS
TYPE integers IS ARRAY (0 TO 12) OF INTEGER;
PROCEDURE apply_data (SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0);
CONSTANT values : IN integers;
CONSTANT period : IN TIME) IS
VARIABLE j : INTEGER;
VARIABLE tmp, pos : INTEGER := 0;
VARIABLE buf : BIT_VECTOR (3 DOWNTO 0);
BEGIN
FOR i IN 0 TO 12 LOOP
tmp := values (i);
j := 0;
WHILE j <= 3 LOOP
IF (tmp MOD 2 = 1) THEN
buf (j) := '1';
ELSE buf (j) := '0';
END IF;
tmp := tmp / 2;
j := j + 1;
END LOOP;
target <= TRANSPORT buf AFTER i * period;
END LOOP;
END apply_data;
COMPONENT comp4 PORT (a, b : IN bit_vector (3 DOWNTO 0);
gt, eq, lt : IN BIT;
a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(structural);
SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0);
SIGNAL eql, lss, gtr : BIT;
SIGNAL vdd : BIT := '1';
SIGNAL gnd : BIT := '0';
BEGIN
a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss);
apply_data (a, 00&15&15&14&14&14&14&10&00&15&00&00&15, 500 NS);
apply_data (b, 00&14&14&15&15&12&12&12&15&15&15&00&00, 500 NS);
END procedural;
FIGURE 6. 4
Procedural architecture of nibble_comparator.
|
TIME (NS) |
SIGNALS |
||||
|
a(3:0) |
b(3:0) |
gtr |
eql |
lss |
|
|
0 |
"0000" |
"0000" |
'0' |
'0' |
'0' |
|
48 |
...... |
...... |
... |
'1' |
... |
|
500 |
"1111" |
"1110" |
... |
... |
... |
|
548 |
...... |
...... |
'1' |
'0' |
... |
|
1500 |
"1110" |
"1111" |
... |
... |
... |
|
1548 |
...... |
...... |
'0' |
... |
'1' |
|
2500 |
...... |
"1100" |
... |
... |
... |
|
2536 |
...... |
...... |
'1' |
... |
'0' |
|
3500 |
"1010" |
...... |
... |
... |
... |
|
3524 |
...... |
...... |
'0' |
... |
'1' |
|
4000 |
"0000" |
"1111" |
... |
... |
... |
|
4500 |
"1111" |
...... |
... |
... |
... |
|
4548 |
...... |
...... |
... |
'1' |
'0' |
|
5000 |
"0000" |
...... |
... |
... |
... |
|
5012 |
...... |
...... |
... |
'0' |
'1' |
|
5500 |
...... |
"0000" |
... |
... |
... |
|
5548 |
...... |
...... |
... |
'1' |
'0' |
|
6000 |
"1111" |
...... |
... |
... |
... |
|
6012 |
...... |
...... |
'1' |
'0' |
... |
FIGURE 6. 5
Simulation report resulting from the procedural test bench. All events are observed.
FIGURE 6. 6
Details of a subprogram body.
FIGURE 6. 7
Loop statement with FOR iteration scheme.
FIGURE 6. 8
Details of the If statement of apply_data procedure.
PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS
VARIABLE result: INTEGER;
BEGIN
result := 0;
FOR i IN bin'RANGE LOOP
IF bin(i) = '1' THEN
result := result + 2**i;
END IF;
END LOOP;
int := result;
END bin2int;
FIGURE 6. 9
Procedure for binary to integer conversion.
PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS VARIABLE tmp : INTEGER;
BEGIN
tmp := int;
FOR i IN 0 TO (bin'LENGTH - 1) LOOP
IF (tmp MOD 2 = 1) THEN
bin (i) := '1';
ELSE bin (i) := '0';
END IF;
tmp := tmp / 2;
END LOOP;
END int2bin;
FIGURE 6. 10
Procedure for integer to binary conversion.
PROCEDURE apply_data (
SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0);
CONSTANT values : IN integers;
CONSTANT period : IN TIME)
IS VARIABLE buf : BIT_VECTOR (3 DOWNTO 0);BEGIN FOR i IN 0 TO 12 LOOP int2bin (values(i), buf); target <= TRANSPORT buf AFTER i * period;
END LOOP;
END apply_data;
FIGURE 6. 11
Another version of apply_data procedure. This version takes advantage of the int2bin procedure.
FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER;BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i;
END IF;
END LOOP;
RETURN result;
END to_integer;
FIGURE 6. 12
Binary to integer conversion function.
PACKAGE simple_gates IS
COMPONENT n1
PORT (i1: IN BIT; o1: OUT BIT);
END COMPONENT;
COMPONENT n2
PORT (i1: i2: IN BIT; o1: OUT BIT);
END COMPONENT;
COMPONENT n3
PORT (i1, i2, i3: IN BIT; o1: OUT BIT);
END COMPONENT;
END simple_gates;
FIGURE 6. 13
A package declaration containing component declarations of simple gates.
USE WORK.simple_gates.ALL;
ARCHITECTURE gate_level OF bit_comparator IS
FOR ALL : n1 USE ENTITY WORK.inv (single_delay); FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay);
FOR ALL : n3 USE ENTITY WORK.nand3 (single_delay);
-- Intermediate signals
SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;
BEGIN
-- a_gt_b output
g0 : n1 PORT MAP (a, im1);
g1 : n1 PORT MAP (b, im2);
g2 : n2 PORT MAP (a, im2, im3);
g3 : n2 PORT MAP (a, gt, im4);
g4 : n2 PORT MAP (im2, gt, im5);
g5 : n3 PORT MAP (im3, im4, im5, a_gt_b);
-- a_eq_b output
g6 : n3 PORT MAP (im1, im2, eq, im6);
g7 : n3 PORT MAP (a, b, eq, im7);
g8 : n2 PORT MAP (im6, im7, a_eq_b);
-- a_lt_b output
g9 : n2 PORT MAP (im1, b, im8);
g10 : n2 PORT MAP (im1, lt, im9);
g11 : n2 PORT MAP (b, lt, im10);
g12 : n3 PORT MAP (im8, im9, im10, a_lt_b);
END gate_level;
FIGURE 6. 14
Using package of simple gates in gate_level of bit_comparator.
USE
WORK.simple_gates.n1,
WORK.simple_gates.n2,
WORK.simple_gates.n3,
.
-- n1, n2 and n3 component declarations are visible
.
FIGURE 6. 15
An alternative application of the use clause.
PACKAGE basic_utilities IS TYPE integers IS ARRAY (0 TO 12) OF INTEGER;
FUNCTION fgl (w, x, gl : BIT) RETURN BIT;
FUNCTION feq (w, x, eq : BIT) RETURN BIT;
PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER);
PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR);
PROCEDURE apply_data (
SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0);
CONSTANT values : IN integers; CONSTANT period : IN TIME);
FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER;END basic_utilities;
FIGURE 6.16a
The basic_utilities package declaration.
PACKAGE BODY basic_utilities IS FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS
BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl;FUNCTION feq (w, x, eq : BIT) RETURN BIT IS BEGIN
RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq);
END feq;
PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS
VARIABLE result: INTEGER;
BEGIN
result := 0;
FOR i IN bin'RANGE LOOP
IF bin(i) = '1' THEN
result := result + 2**i;
END IF;
END LOOP;
int := result;
END bin2int;
PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS
VARIABLE tmp : INTEGER;
VARIABLE buf : BIT_VECTOR (bin'RANGE);
BEGIN
tmp := int;
FOR i IN 0 TO (bin'LENGTH - 1) LOOP
IF (tmp MOD 2 = 1) THEN
bin (i) := '1';
ELSE bin (i) := '0'; END IF;
tmp := tmp / 2;
END LOOP;
END int2bin;
PROCEDURE apply_data (
SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0);
CONSTANT values : IN integers; CONSTANT period : IN TIME) IS
VARIABLE buf : BIT_VECTOR (3 DOWNTO 0);
BEGIN
FOR i IN 0 TO 12 LOOP
int2bin (values(i), buf);
target <= TRANSPORT buf AFTER i * period;
END LOOP;
END apply_data;
FUNCTION to_integer (bin : BIT_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER; BEGIN result := 0; FOR i IN bin'RANGE LOOP IF bin(i) = '1' THEN result := result + 2**i;
END IF; END LOOP;
RETURN result;
END to_integer;
END basic_utilities;
FIGURE 6.16b
The basic_utilities package body. FIGURE 6. 16 basic_utilities package. (a) declaration, (b) body.USE WORK.basic_utilities.ALL;
ARCHITECTURE functional OF bit_comparator IS
BEGIN
a_gt_b <= fgl (a, b, gt) AFTER 12 NS;
a_eq_b <= feq (a, b, eq) AFTER 12 NS;
a_lt_b <= fgl (b, a, lt) AFTER 12 NS;
END functional;
FIGURE 6. 17
Using functions of the basic_utilities package.
USE WORK.basic_utilities.ALL;
ARCHITECTUR procedural OF nibble_comparator_test_bench IS
COMPONENT comp4 PORT (
a, b : IN bit_vector (3 DOWNTO 0); gt, eq, lt : IN BIT;
a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(structural);
SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0);
SIGNAL eql, lss, gtr : BIT;
SIGNAL vdd : BIT := '1';
SIGNAL gnd : BIT := '0';
BEGIN
a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss);
apply_data (a, 0&15&15&14&14&14&14&10&00&15&00&00&15, 500 NS);
apply_data (b, 0&14&14&15&15&12&12&12&15&15&15&00&00, 500 NS);
END procedural;
FIGURE 6. 18
Using procedures of the basic_utilities package.
ENTITY inv_t IS
GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS);
PORT (i1 : IN BIT; o1 : OUT BIT);
END inv_t;
--
ARCHITECTURE average_delay OF inv_t IS
BEGIN
o1 <= NOT i1 AFTER (tplh + tphl) / 2;
END average_delay;
ENTITY nand2_t IS
GENERIC (tplh : TIME := 6 NS; tphl : TIME := 4 NS);
PORT (i1, i2 : IN BIT; o1 : OUT BIT);
END nand2_t;
--
ARCHITECTURE average_delay OF nand2_t IS
BEGIN
o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2;
END average_delay;
ENTITY nand3_t IS
GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5 NS);
PORT (i1, i2, i3 : IN BIT; o1 : OUT BIT);
END nand3_t;
--
ARCHITECTURE average_delay OF nand3_t IS
BEGIN
o1 <= NOT ( i1 AND i2 AND i3 ) AFTER (tplh + tphl) / 2;
END average_delay;
FIGURE 6. 19
Parametrized gate models.
FIGURE 6. 20
Details of the entity declaration of inverter with generics.
FIGURE 6. 21
Interface aspects of inv_t, nand2_t, and nand3_t.
ARCHITECTURE default_delay OF bit_comparator IS
COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT;
COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT;
COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT);
END COMPONENT;
FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay);
FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay);
FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay);
-- Intermediate signals
SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;
BEGIN
-- a_gt_b output
g0 : n1 PORT MAP (a, im1);
g1 : n1 PORT MAP (b, im2);
g2 : n2 PORT MAP (a, im2, im3);
g3 : n2 PORT MAP (a, gt, im4);
g4 : n2 PORT MAP (im2, gt, im5);
g5 : n3 PORT MAP (im3, im4, im5, a_gt_b);
-- a_eq_b output
g6 : n3 PORT MAP (im1, im2, eq, im6);
g7 : n3 PORT MAP (a, b, eq, im7);
g8 : n2 PORT MAP (im6, im7, a_eq_b);
-- a_lt_b output
g9 : n2 PORT MAP (im1, b, im8);
g10 : n2 PORT MAP (im1, lt, im9);
g11 : n2 PORT MAP (b, lt, im10);
g12 : n3 PORT MAP (im8, im9, im10, a_lt_b);
END default_delay;
FIGURE 6. 22
Using default values for the generics of logic gates.
ARCHITECTURE fixed_delay OF bit_comparator IS
COMPONENT n1
GENERIC (tplh, tphl : TIME); PORT (i1: IN BIT; o1: OUT BIT);
END COMPONENT;
COMPONENT n2
GENERIC (tplh, tphl : TIME); PORT (i1, i2: IN BIT; o1: OUT BIT);
END COMPONENT;
COMPONENT n3
GENERIC (tplh, tphl : TIME); PORT (i1, i2, i3: IN BIT; o1: OUT BIT);
END COMPONENT;
FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay);
FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay);
FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay);
-- Intermediate signals
SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;
BEGIN
-- a_gt_b output
g0 : n1 GENERIC MAP (2 NS, 4 NS) PORT MAP (a, im1);
g1 : n1 GENERIC MAP (2 NS, 4 NS) PORT MAP (b, im2);
g2 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (a, im2, im3);
g3 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (a, gt, im4);
g4 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im2, gt, im5);
g5 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im3, im4, im5, a_gt_b);
-- a_eq_b output
g6 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im1, im2, eq, im6);
g7 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (a, b, eq, im7);
g8 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im6, im7, a_eq_b);
-- a_lt_b output
g9 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im1, b, im8);
g10 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im1, lt, im9);
g11 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (b, lt, im10);
g12 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im8, im9, im10, a_lt_b);
END fixed_delay;
FIGURE 6. 23
Associating fixed values with the generics of logic gates.
FIGURE 6. 24
Component instantiation statement with generic map aspect.
ENTITY bit_comparator_t IS
GENERIC (tplh1, tplh2, tplh3, tphl1, tphl2, tphl3 : TIME);
PORT (a, b, -- data inputs
gt, -- previous greater than
eq, -- previous equal
lt : IN BIT; -- previous less than
a_gt_b, -- greater
a_eq_b, -- equal
a_lt_b : OUT BIT); -- less than
END bit_comparator_t;
(a)
ARCHITECTURE passed_delay OF bit_comparator_t IS
COMPONENT n1
GENERIC (tplh, tphl : TIME);
PORT (i1: IN BIT; o1: OUT BIT);
END COMPONENT;
COMPONENT n2
GENERIC (tplh, tphl : TIME);
PORT (i1, i2: IN BIT; o1: OUT BIT);
END COMPONENT;
COMPONENT n3
GENERIC (tplh, tphl : TIME);
PORT (i1, i2, i3: IN BIT; o1: OUT BIT);
END COMPONENT;
FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay);
FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay);
FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay);
-- Intermediate signals
SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;
BEGIN
-- a_gt_b output
g0 : n1 GENERIC MAP (tplh1, tphl1) PORT MAP (a, im1);
g1 : n1 GENERIC MAP (tplh1, tphl1) PORT MAP (b, im2);
g2 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (a, im2, im3);
g3 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (a, gt, im4);
g4 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im2, gt, im5);
g5 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (im3, im4, im5, a_gt_b);
-- a_eq_b output
g6 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (im1, im2, eq, im6);
g7 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (a, b, eq, im7);
g8 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im6, im7, a_eq_b);
-- a_lt_b output
g9 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im1, b, im8);
g10 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (im1, lt, im9);
g11 : n2 GENERIC MAP (tplh2, tphl2) PORT MAP (b, lt, im10);
g12 : n3 GENERIC MAP (tplh3, tphl3) PORT MAP (im8, im9, im10, a_lt_b);
END passed_delay;
(b)
FIGURE 6. 25
A bit comparator with timing parameters (a) entity declaration, (b) passing generics of bit comparator to its components.
FIGURE 6. 26
Composition aspect of bit_comparator_t. Dotted lines with arrows indicate generics.
ARCHITECTURE iterative OF nibble_comparator IS
COMPONENT comp1
GENERIC(tplh1 : TIME := 2 NS; tplh2 :TIME := 3 NS; tplh3 : TIME := 4 ns;
tplh1 : TIME := 4 NS; tplh2 :TIME := 5 NS; tplh3 : TIME := 6 ns;
PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
FOR ALL : comp1 USE ENTITY WORK.bit_comparator_t (passed_delay);
SIGNAL im : BIT_VECTOR ( 0 TO 8);
BEGIN
c0: comp1 PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2));
c1to2: FOR i IN 1 TO 2 GENERATE
c: comp1 PORT MAP
(a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) );
END GENERATE;
c3: comp1 PORT MAP (a(3), b(3), im(6), im(7), im(8),
a_gt_b, a_eq_b, a_lt_b);
END iterative;
FIGURE 6. 27
Passing default values of local generics to the generics of bit_comparator_t.
ARCHITECTURE iterative OF nibble_comparator IS
. . .
BEGIN
c0: comp1
GENERIC MAP (OPEN, OPEN, 8 NS, OPEN, OPEN, 10 NS)
PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2));
. . .
END iterative;
FIGURE 6. 28
Associating constants with some of generics of bit_comparator_t, and using defaults for others.
ARCHITECTURE iterative OF nibble_comparator IS
. . .
BEGIN
c0: comp1
GENERIC MAP (tplh3 => 8 NS, tphl3 => 10 NS)
PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2));
. . .
END iterative;
FIGURE 6. 29
Using named association in the generic association list of comp1.
USE WORK.basic_utilities.ALL;
ARCHITECTURE customizable OF nibble_comarator_test_bench IS
COMPONENT comp4 PORT (
a, b : IN BIT_VECTOR (3 DOWNTO 0); gt, eq, lt : IN BIT;
a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0);
SIGNAL eql, lss, gtr : BIT;
SIGNAL vdd : BIT := '1';
SIGNAL gnd : BIT := '0';
BEGIN
a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss);
apply_data (a, (0,15,15,14,14,14,14,10,00,15,00,00,15), 500 NS);
apply_data (b, (0,14,14,15,15,12,12,12,15,15,15,00,00), 500 NS);
END customizable;
FIGURE 6. 30
A customizable test bench.
FIGURE 6. 31
Configuring customizable for testing structural architecture of nibble_comparator.
FIGURE 6. 32
Composition aspect for functional configuration declaration, configuring customizable test bench.
USE WORK.ALL;
CONFIGURATION average_delay OF nibble_comparator_test_bench IS
FOR customizable
FOR a1 : comp4
USE ENTITY WORK.nibble_comparator(iterative);
END FOR;
END FOR;
END average_delay;
FIGURE 6. 33
Configuring customizable for testing iterative architecture of nibble_comparator.
FIGURE 6. 34
Details of configuration declaration.
ARCHITECTURE flexible OF nibble_comparator IS
COMPONENT comp1
PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
SIGNAL im : BIT_VECTOR ( 0 TO 8);
BEGIN
c0: comp1 PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2));
c1to2: FOR i IN 1 TO 2 GENERATE
c: comp1 PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1),
im(i*3+0), im(i*3+1), im(i*3+2) );
END GENERATE;
c3: comp1 PORT MAP (a(3), b(3), im(6), im(7), im(8),
a_gt_b, a_eq_b, a_lt_b);
END flexible;
FIGURE 6. 35
A general purpose nibble_comparator.
FIGURE 6. 36
Composition aspect for configuring customizable test bench for testing default_delay bit_comparator.
USE WORK.ALL;
CONFIGURATION default_bit_level OF nibble_comparator_test_bench IS
FOR customizable
FOR a1 : comp4
USE ENTITY WORK.nibble_comparator(flexible);
FOR flexible
FOR c0, c3: comp1
USE ENTITY WORK.bit_comparator (default_delay);
END FOR;
FOR c1to2
FOR c: comp1
USE ENTITY WORK.bit_comparator (default_delay);
END FOR;
END FOR;
END FOR;
END FOR;
END FOR;
END default_bit_level;
FIGURE 6. 37
Configuration declaration for configuring customizable test bench for testing default_delay bit_comparator.
USE WORK.ALL;
CONFIGURATION fixed_bit_level OF nibble_comparator_test_bench IS
FOR customizable
FOR a1 : comp4
USE ENTITY WORK.nibble_comparator(flexible);
FOR flexible
FOR c0, c3: comp1
USE ENTITY WORK.bit_comparator (fixed_delay);
END FOR;
FOR c1to2
FOR c: comp1
USE ENTITY WORK.bit_comparator (fixed_delay);
END FOR;
END FOR;
END FOR;
END FOR;
END FOR;
END fixed_bit_level;
FIGURE 6. 38
Configuring customizable test bench for testing the fixed_delay architecture of bit_comparator.
FIGURE 6. 39
Composition aspect of the passed_bit_level configuration of the test bench for testing passed_delay architecture of bit_comparator_t.
USE WORK.ALL;
CONFIGURATION passed_bit_level OF nibble_comparator_test_bench IS
FOR customizable
FOR a1 : comp4
USE ENTITY WORK.nibble_comparator(flexible);
FOR flexible
FOR c0, c3: comp1
USE ENTITY WORK.bit_comparator_t (passed_delay)
GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS,
tplh3 => 4 NS, tphl1 => 4 NS,
tphl2 => 5 NS, tphl3 => 6 NS);
END FOR;
FOR c1to2
FOR c: comp1
USE ENTITY WORK.bit_comparator_t (passed_delay)
GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS,
tplh3 => 4 NS, tphl1 => 4 NS,
tphl2 => 5 NS, tphl3 => 6 NS);
END FOR;
END FOR;
END FOR;
END FOR;
END FOR;
END passed_bit_level;
FIGURE 6. 40
Using configuration declarations for component bindings, and specification of generic parameters.
FIGURE 6. 41
Details of a block configuration enclosing component configurations and other block configurations.
ARCHITECTURE partially_flexible OF nibble_comparator IS
COMPONENT comp1
PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
FOR ALL:comp1 USE ENTITY WORK.bit_comparator_t (passed_delay);
SIGNAL im : BIT_VECTOR ( 0 TO 8 );
BEGIN
c0: comp1 PORT MAP ( . . . );
c1to2 : FOR i IN 1 TO 2 GENERATE
c: comp1 PORT MAP ( . . . );
END GENERATE;
c3: comp1 PORT MAP ( . . . );
END partially_flexible;
FIGURE 6. 42
Primary binding indication illustration.
USE WORK.ALL;
CONFIGURATION incremental OF nibble_comparator_test_bench IS
FOR customizable
FOR a1 : comp4 USE ENTITY WORK.nibble_comparator (partially_flexible);
FOR flexible
FOR c0, c3: comp1
GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS,
tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS);
END FOR;
FOR c1to2
FOR c: comp1
GENERIC MAP (tplh1 => 2 NS, tplh2 => 3 NS,
tplh3 => 4 NS, tphl1 => 4 NS, tphl2 => 5 NS, tphl3 => 6 NS);
END FOR;
END FOR;
END FOR;
END FOR;
END FOR;
END incremental;
FIGURE 6. 43
Incremental binding indication illustration.
ENTITY sr_latch IS PORT (s, r, c : IN BIT; q : OUT BIT);
END sr_latch;
--
ARCHITECTURE gate_level OF sr_latch IS
COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT;
SIGNAL im1, im2, im3, im4 : BIT;
BEGIN
g1 : n2 PORT MAP (s, c, im1);
g2 : n2 PORT MAP (r, c, im2);
g3 : n2 PORT MAP (im1, im4, im3);
g4 : n2 PORT MAP (im3, im2, im4);
q <= im3;
END gate_level;
FIGURE 6.44
Unbound VHDL description of set-reset latch.
ENTITY d_latch IS PORT (d, c : IN BIT; q : OUT BIT);
END d_latch;
--
ARCHITECTURE sr_based OF d_latch IS
COMPONENT sr PORT (s, r, c : IN BIT; q : OUT BIT); END COMPONENT;
COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT;
SIGNAL dbar : BIT;
BEGIN
c1 : sr PORT MAP (d, dbar, c, q);
c2 : n1 PORT MAP (d, dbar);
END sr_based;
FIGURE 6.45
Unbound VHDL description of a D-latch.
ENTITY d_register IS
PORT (d : IN BIT_VECTOR; c : IN BIT; q : OUT BIT_VECTOR);
END d_register;
--
ARCHITECTURE latch_based OF d_register IS
COMPONENT dl PORT (d, c : IN BIT; q : OUT BIT); END COMPONENT;
BEGIN
dr : FOR i IN d'RANGE GENERATE
di : dl PORT MAP (d(i), c, q(i));
END GENERATE;
END latch_based;
FIGURE 6.46
Unbound VHDL description for an n-bit latch.
FIGURE 6.47
Composition aspect for configuring the latch_based architecture of d_register.
FIGURE 6.48
Configuring d_register for using average_delay gates.
|
Block No. |
Configuration Type |
PURPOSE Visibility or Binding to: |
Becomes Visible by: |
|
|
1 |
Configuration Declaration |
Main |
- |
- |
|
2 |
Block Configuration |
Visibility |
latch_based ARCHITECTURE Figure 6.46 |
1 |
|
3 |
Block Configuration |
Visibility |
dr GENERATE STATEMENT Figure 6.46 |
1, 2 |
|
4 |
Component Configuration |
Binding |
di instance of dlFigure 6.46 |
1, 2, 3 |
|
5 |
Block Configuration |
Visibility |
sr_based ARCHITECTURE Figure 6.45 |
1, 2, 3, 4 |
|
6 |
Component Configuration |
Binding |
c1 instance of srFigure 6.45 |
1, 2, 3, 4, 5 |
|
7 |
Component Configuration |
Binding |
c2 instance of srFigure 6.45 |
1, 2, 3, 4, 5 |
|
8 |
Block Configuration |
Visibility |
gate_level ARCHITECTURE Figure 6.44 |
1, 2, 3, 4, 5, 6 |
|
9 |
Component Configuration |
Binding |
instances g2, g4 of n2 Figure 6.44 |
1, 2, 3, 4, 5, 6, 8 |
|
10 |
Component Configuration |
Binding |
instances g1, g3 of n2 Figure 6.44 |
1, 2, 3, 4, 5, 6, 8 |
FIGURE 6.49
Analyzing configuration constructs of the average_gate_delay configuration of d_register.
USE WORK.ALL;
CONFIGURATION single_gate_delay OF d_register IS
FOR latch_based
FOR dr
FOR di : dl
USE ENTITY WORK.d_latch(sr_based);
FOR sr_based
FOR c1 : sr
USE ENTITY WORK.sr_latch(gate_level);
FOR gate_level
FOR g2, g4 : n2
USE ENTITY WORK.nand3(single_delay)
PORT MAP (i1, i1, i2, o1);
END FOR;
FOR g1, g3 : n2
USE ENTITY WORK.nand2(single_delay);
END FOR;
END FOR;
END FOR;
FOR c2 : n1
USE ENTITY WORK.inv(single_delay);
END FOR;
END FOR;
END FOR;
END FOR;
END FOR;
END single_gate_delay;
FIGURE 6.50
Configuring d_register for using single_delay architectures of inv and nand2.
ARCHITECTURE single OF d_register_test_bench IS
COMPONENT reg PORT (d : IN BIT_VECTOR (7 DOWNTO 0); c : IN BIT;
q : OUT BIT_VECTOR (7 DOWNTO 0) );
END COMPONENT;
FOR r8 : reg USE CONFIGURATION WORK.single_gate_delay;
SIGNAL data, outdata : BIT_VECTOR (7 DOWNTO 0);
SIGNAL clk : BIT;
BEGIN
r8: reg PORT MAP (data, clk, outdata);
data <= X"00", X"AA" AFTER 0500 NS, X"55" AFTER 1500 NS;
clk <= '0', '1' AFTER 0200 NS, '0' AFTER 0300 NS,
'1' AFTER 0700 NS, '0' AFTER 0800 NS,
'1' AFTER 1700 NS, '0' AFTER 1800 NS;
END single;
FIGURE 6.51
Test bench for the single_delay architecture of d_register.
FIGURE 6.52
Parity generator/checker circuit.
ENTITY xor2_t IS
GENERIC (tplh : TIME := 9 NS; tphl : TIME := 7 NS);
PORT (i1, i2 : IN BIT; o1 : OUT BIT);
END xor2_t;
--
ARCHITECTURE average_delay OF xor2_t IS
BEGIN
o1 <= i1 XOR i2 AFTER (tplh + tphl) / 2;
END average_delay;
----
ENTITY inv_t IS
GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS);
PORT (i1 : IN BIT; o1 : OUT BIT);
END inv_t;
--
ARCHITECTURE average_delay OF inv_t IS
BEGIN
o1 <= NOT i1 AFTER (tplh + tphl) / 2;
END average_delay;
FIGURE 6.53
Timed XOR and INV gates.
ENTITY parity IS
PORT (a : IN BIT_VECTOR (7 DOWNTO 0); odd, even : OUT BIT);
END parity;
--
ARCHITECTURE iterative OF parity IS
COMPONENT x2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT;
COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT;
SIGNAL im : BIT_VECTOR ( 0 TO 6 );
BEGIN
first: x2 PORT MAP (a(0), a(1), im(0));
middle: FOR i IN 1 TO 6 GENERATE
m: x2 PORT MAP (im(i-1), a(i+1), im(i));
END GENERATE;
last: odd <= im(6);
inv: n1 PORT MAP (im(6), even);
END iterative;
FIGURE 6.54
Parity circuit description.
CONFIGURATION parity_binding OF parity IS
FOR iterative
FOR first : x2
USE ENTITY WORK.xor2_t (average_delay)
GENERIC MAP (5 NS, 5 NS);
END FOR;
FOR middle (1 TO 5)
FOR m : x2
USE ENTITY WORK.xor2_t (average_delay)
GENERIC MAP (5 NS, 5 NS);
END FOR;
END FOR;
FOR middle ( 6)
FOR m : x2
USE ENTITY WORK.xor2_t (average_delay)
GENERIC MAP (6 NS, 7 NS);
END FOR;
END FOR;
FOR inv : n1
USE ENTITY WORK.inv_t (average_delay) GENERIC MAP (5 NS, 5 NS);
END FOR;
END FOR;
END parity_binding;
FIGURE 6.55
Parity circuit configuration declaration.
|
Value |
Representing |
|
'U' |
Uninitialized |
|
'X' |
Forcing Unknown |
|
'0' |
Forcing 0 |
|
'1' |
Forcing 1 |
|
'Z' |
High Impedance |
|
'W' |
Weak Unknown |
|
'L' |
Weak 0 |
|
'H' |
Weak 1 |
|
'-' |
Don't care |
FIGURE 6.56
Std_logic logic value system.
|
. |
U |
X |
0 |
1 |
Z |
W |
L |
H |
- |
|
U |
'U' |
'U' |
'0' |
'U' |
'U' |
'U' |
'0' |
'U' |
'U’ |
|
X |
'U' |
'X' |
'0' |
'X' |
'X' |
'X' |
'0' |
'X' |
'X' |
|
0 |
'0' |
'0' |
'0' |
'0' |
'0' |
'0' |
'0' |
'0' |
'0' |
|
1 |
'U' |
'X' |
'0' |
'1' |
'X' |
'X' |
'0' |
'1' |
'X’ |
|
Z |
'U' |
'X' |
'0' |
'X' |
'X' |
'X' |
'0' |
'X' |
'X' |
|
W |
'U' |
'X' |
'0' |
'X' |
'X' |
'X' |
'0' |
'X' |
'X' |
|
L |
'0' |
'0' |
'0' |
'0' |
'0' |
'0' |
'0' |
'0' |
'0' |
|
H |
'U' |
'X' |
'0' |
'1' |
'X' |
'X' |
'0' |
'1' |
'X' |
|
- |
'U' |
'X' |
'0' |
'X' |
'X' |
'X' |
'0' |
'X' |
'X' |
FIGURE 6.57
AND table for std_logic type.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
ENTITY nand2_t IS
GENERIC (tplh : TIME := 6 NS; tphl : TIME := 4 NS);
PORT (i1, i2 : IN std_logic; o1 : OUT std_logic);
END nand2_t;
--
ARCHITECTURE average_delay_mvla OF nand2_t IS
BEGIN
o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2;
END average_delay_mvla;
FIGURE 6.58
A two-input NAND gate in std_logic value system.
|
LIBRARY ls7400 User: John Designer |
Date |
|
|
simple_gates |
PACKAGE DECLARATION |
June 9, 1997 |
|
inv |
ENTITY |
June 8, 1997 |
|
inv(single_delay) |
ARCHITECTURE |
June 8, 1997 |
|
nand2 |
ENTITY |
June 6, 1997 |
|
nand2(single_delay) |
ARCHITECTURE |
June 6, 1997 |
|
nand3 |
ENTITY |
June 6, 1997 |
|
nand3(single_delay) |
ARCHITECTURE |
June 6, 1997 |
FIGURE 6.59
Directory of ls7400 library containing package declarations, entities and architectures are been compiled into it.
LIBRARY ls7400;
USE ls7400.simple_gates.ALL;
FIGURE 6.60
Making all declarations of simple_gates package of ls7400 library available.
LIBRARY ls7400;
USE ls7400.simple_gates.ALL;
--
ARCHITECTURE gate_level OF sr_latch IS
SIGNAL im1, im2, im3, im4 : BIT;
BEGIN
g1 : n2 PORT MAP (s, c, im1);
g2 : n2 PORT MAP (r, c, im2);
g3 : n2 PORT MAP (im1, im4, im3);
g4 : n2 PORT MAP (im3, im2, im4);
q <= im3;
END gate_level;
FIGURE 6.61
Using component declarations of simple_gates package of ls7400 library for description of set-reset latch.
LIBRARY ls7400;
USE ls7400.ALL;
FIGURE 6.62
Making all entities and architectures of the ls7400 library available.
LIBRARY ls7400;
USE ls7400.ALL;
.
.
… FOR g1, g3 : n2
… USE ENTITY ls7400.nand2 (single_delay);
… END FOR;
FIGURE 6.63
Using a component configuration for associating g1 and g3 instances of n2 of Figure 6.61 with nand2 of ls7400.