VLSI Implementation of Parwan, Fabricated at Massachusetts Microelectronics Center.

Page and Offset Parts of Parwan addresses.

Summary of Parwan instructions.

Parwan instruction opcodes.

Addressing in full-address instructions.

Addressing in page-address instructions.

A branch instruction.

An example for the execution of jsr. Memory and pc, before and after jsr.

An example for indirect addressing in Parwan.

0:15 cla -- clear accumulator

0:16 asl -- clears carry

0:17 add, i 4:00 -- add bytes

0:19 sta 4:03 -- store partial sum

0:1B lda 4:00 -- load pointer

0:1D add 4:02 -- increment pointer

0:1F sta 4:00 -- store pointer back

0:21 lda 4:01 -- load count

0:23 sub 4:02 -- decrement count

0:25 bra_z :2D -- end if zero count

0:27 sta 4:01 -- store count back

0:29 lda 4:03 -- get partial sum

0:2B jmp 0:17 -- go for next byte

0:2D nop -- adding completed

An example program for Parwan CPU.

LIBRARY cmos;

USE cmos.basic_utilities.ALL;

--

PACKAGE par_utilities IS

FUNCTION "XOR" (a, b : qit) RETURN qit ;

FUNCTION "AND" (a, b : qit_vector) RETURN qit_vector;

FUNCTION "OR" (a, b : qit_vector) RETURN qit_vector;

FUNCTION "NOT" (a : qit_vector) RETURN qit_vector;

--

SUBTYPE nibble IS qit_vector (3 DOWNTO 0);

SUBTYPE byte IS qit_vector (7 DOWNTO 0);

SUBTYPE twelve IS qit_vector (11 DOWNTO 0);

--

SUBTYPE wired_nibble IS wired_qit_vector (3 DOWNTO 0);

SUBTYPE wired_byte IS wired_qit_vector (7 DOWNTO 0);

SUBTYPE wired_twelve IS wired_qit_vector (11 DOWNTO 0);

--

SUBTYPE ored_nibble IS ored_qit_vector (3 DOWNTO 0);

SUBTYPE ored_byte IS ored_qit_vector (7 DOWNTO 0);

SUBTYPE ored_twelve IS ored_qit_vector (11 DOWNTO 0);

--

CONSTANT zero_4 : nibble := "0000";

CONSTANT zero_8 : byte := "00000000";

CONSTANT zero_12 : twelve := "000000000000";

--

FUNCTION add_cv (a, b : qit_vector; cin : qit) RETURN qit_vector;

FUNCTION sub_cv (a, b : qit_vector; cin : qit) RETURN qit_vector;

--

FUNCTION set_if_zero (a : qit_vector) RETURN qit;

--

END par_utilities;

PACKAGE BODY par_utilities IS FUNCTION "XOR" (a, b : qit) RETURN qit IS

CONSTANT qit_xor_table : qit_2d := (

('0','1','1','X'),

('1','0','0','X'),

('1','0','0','X'),

('X','X','X','X'));

BEGIN

RETURN qit_xor_table (a, b);

END "XOR";

FUNCTION "AND" (a,b : qit_vector) RETURN qit_vector IS

VARIABLE r : qit_vector (a'RANGE);

BEGIN

loop1: FOR i IN a'RANGE LOOP

r(i) := a(i) AND b(i);

END LOOP loop1;

RETURN r;

END "AND";

--

FUNCTION "OR" (a,b: qit_vector) RETURN qit_vector IS

VARIABLE r: qit_vector (a'RANGE);

BEGIN

loop1: FOR i IN a'RANGE LOOP

r(i) := a(i) OR b(i);

END LOOP loop1;

RETURN r;

END "OR";

--

FUNCTION "NOT" (a: qit_vector) RETURN qit_vector IS

VARIABLE r: qit_vector (a'RANGE);

BEGIN

loop1: FOR i IN a'RANGE LOOP

r(i) := NOT a(i);

END LOOP loop1;

RETURN r;

END "NOT";

-- extra r bits : msb: overflow, next to msb: carry

VARIABLE a_sign, b_sign: qit; BEGIN a_sign := a(a'LEFT);

b_sign := b(b'LEFT);

r(0) := a(0) XOR b(0) XOR cin;

c(0) := ((a(0) XOR b(0)) AND cin) OR (a(0) AND b(0));

FOR i IN 1 TO (a'LEFT) LOOP

r(i) := a(i) XOR b(i) XOR c(i-1);

c(i) := ((a(i) XOR b(i)) AND c(i-1)) OR (a(i) AND b(i));

END LOOP;

r(a'LEFT+1) := c(a'LEFT);

IF a_sign = b_sign AND r(a'LEFT) /= a_sign THEN

r(a'LEFT+2) := '1'; --overflow

ELSE

r(a'LEFT+2) := '0';

END IF;

RETURN r;

END add_cv;

FUNCTION sub_cv (a, b : qit_vector; cin : qit) RETURN qit_vector IS

VARIABLE not_b : qit_vector (b'LEFT DOWNTO 0);

VARIABLE not_c : qit;

VARIABLE r : qit_vector (a'LEFT + 2 DOWNTO 0);

BEGIN

not_b := NOT b;

not_c := NOT cin;

r := add_cv (a, not_b, not_c);

RETURN r;

END sub_cv;

FUNCTION set_if_zero (a : qit_vector) RETURN qit IS

VARIABLE zero : qit := '1';

BEGIN

FOR i IN a'RANGE LOOP

IF a(i) /= '0'

THEN zero := '0'; EXIT;

END IF;

END LOOP;

RETURN zero;

END set_if_zero;

END par_utilities;

LIBRARY cmos;USE cmos.basic_utilities.ALL;--PACKAGE par_parameters IS CONSTANT single_byte_instructions : qit_vector (3 DOWNTO 0) := "1110"; CONSTANT cla : qit_vector (3 DOWNTO 0) := "0001";

CONSTANT cma : qit_vector (3 DOWNTO 0) := "0010";

CONSTANT cmc : qit_vector (3 DOWNTO 0) := "0100";

CONSTANT asl : qit_vector (3 DOWNTO 0) := "1000";

CONSTANT asr : qit_vector (3 DOWNTO 0) := "1001";

CONSTANT jsr : qit_vector (2 DOWNTO 0) := "110";

CONSTANT bra : qit_vector (3 DOWNTO 0) := "1111";

CONSTANT indirect : qit := '1';

CONSTANT jmp : qit_vector (2 DOWNTO 0) := "100";

CONSTANT sta : qit_vector (2 DOWNTO 0) := "101";

CONSTANT lda : qit_vector (2 DOWNTO 0) := "000";

CONSTANT ann : qit_vector (2 DOWNTO 0) := "001";

CONSTANT add : qit_vector (2 DOWNTO 0) := "010";

CONSTANT sbb : qit_vector (2 DOWNTO 0) := "011";

CONSTANT jsr_or_bra : qit_vector (1 DOWNTO 0) := "11";

END par_parameters;

LIBRARY cmos;USE cmos.basic_utilities.ALL;--

LIBRARY par_library;USE par_library.par_utilities.ALL;USE par_library.par_parameters.ALL;--ENTITY par_central_processing_unit IS GENERIC (read_high_time, read_low_time,

write_high_time, write_low_time : TIME := 2 US;

cycle_time : TIME := 4 US);

PORT (clk : IN qit;

interrupt : IN qit;

read_mem, write_mem : OUT qit;

databus : INOUT wired_byte BUS := "ZZZZZZZZ"; adbus : OUT twelve

);

END par_central_processing_unit;

ARCHITECTURE behavioral OF par_central_processing_unit ISBEGIN PROCESS Declare necessary variables; Figure 10.16. BEGIN IF interrupt = '1' THEN Handle interrupt; Figure 10.17.

ELSE -- no interrupt

IF byte1 (7 DOWNTO 4) = single_byte_instructions THEN

ELSE -- two-byte instructions

IF byte1 (7 DOWNTO 5) = jsr THEN

ELSIF byte1 (7 DOWNTO 4) = bra THEN

ELSE -- all other two-byte instructions

IF byte1 (4) = indirect THEN

END IF; -- ends indirect

IF byte1 (7 DOWNTO 5) = jmp THEN

ELSIF byte1 (7 DOWNTO 5) = sta THEN

ELSE -- read operand for lda, and, add, sub

END IF; -- jmp / sta / lda, and, add, sub

END IF; -- jsr / bra / other double-byte instructions

END IF; -- single-byte / double-byte

END IF; -- interrupt / otherwise

END PROCESS;

END behavioral;

VARIABLE pc : twelve;VARIABLE ac, byte1, byte2 : byte;VARIABLE v, c, z, n : qit;VARIABLE temp : qit_vector (9 DOWNTO 0);

pc := zero_12;WAIT FOR cycle_time;

adbus <= pc;read_mem <= '1'; WAIT FOR read_high_time;byte1 := byte (databus);read_mem <= '0'; WAIT FOR read_low_time;pc := inc (pc);

CASE byte1 (3 DOWNTO 0) ISWHEN cla => ac := zero_8;WHEN cma => ac := NOT ac;

IF ac = zero_8 THEN z := '1'; END IF;

n := ac (7);

WHEN cmc =>

c := NOT c;

WHEN asl =>

c := ac (7);

ac := ac (6 DOWNTO 0) & '0';

IF ac = zero_8 THEN z := ‘1’; END IF;

n := ac (7);

IF c /= n THEN v := '1'; END IF;

WHEN asr =>

ac := ac (7) & ac (7 DOWNTO 1);

IF ac = zero_8 THEN z := '1'; END IF;

n := ac (7);

WHEN OTHERS => NULL;

END CASE;

adbus <= pc;read_mem <= '1'; WAIT FOR read_high_time;byte2 := byte (databus);read_mem <= '0'; WAIT FOR read_low_time;pc := inc (pc);

databus <= wired_byte (pc (7 DOWNTO 0) );adbus (7 DOWNTO 0) <= byte2;

write_mem <= '1'; WAIT FOR write_high_time;

write_mem <= '0'; WAIT FOR write_low_time;

databus <= "ZZZZZZZZ";

pc (7 DOWNTO 0) := inc (byte2);

IF ( byte1 (3) = '1' AND v = '1' ) OR ( byte1 (2) = '1' AND c = '1' ) OR ( byte1 (1) = '1' AND z = '1' ) OR ( byte1 (0) = '1' AND n = '1' )

THEN

pc (7 DOWNTO 0) := byte2;

END IF;

adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0);adbus (7 DOWNTO 0) <= byte2;read_mem <= '1'; WAIT FOR read_high_time;byte2 := byte (databus);read_mem <= '0'; WAIT FOR read_low_time;

pc := byte1 (3 DOWNTO 0) & byte2;

adbus <= byte1 (3 DOWNTO 0) & byte2;databus <= wired_byte (ac);write_mem <= '1'; WAIT FOR write_high_time;

write_mem <= '0'; WAIT FOR write_low_time;

databus <= "ZZZZZZZZ";

adbus (11 DOWNTO 8) <= byte1 (3 DOWNTO 0);

adbus (7 DOWNTO 0) <= byte2;

read_mem <= '1'; WAIT FOR read_high_time;

CASE byte1 (7 DOWNTO 5) IS

WHEN lda =>

ac := byte (databus);

WHEN ann =>

ac := ac AND byte (databus);

WHEN add =>

temp := add_cv (ac, byte (databus), c);

ac := temp (7 DOWNTO 0);

c := temp (8);

v := temp (9);

WHEN sbb =>

temp := sub_cv (ac, byte (databus), c);

ac := temp (7 DOWNTO 0);

c := temp (8);

v := temp (9);

WHEN OTHERS => NULL;

END CASE;

IF ac = zero_8 THEN z := '1'; END IF;

n := ac (7);

read_mem <= '0'; WAIT FOR read_low_time;

Timing of control signals.

Operations and flags of alu.

Parwan alu. (a) Logic symbol, (b) one bit gate level hardware.

LIBRARY cmos;USE cmos.basic_utilities.ALL;

--PACKAGE alu_operations IS CONSTANT a_and_b : qit_vector (5 DOWNTO 0) := "000001"; CONSTANT b_compl : qit_vector (5 DOWNTO 0) := "000010";

CONSTANT a_input : qit_vector (5 DOWNTO 0) := "000100";

CONSTANT a_add_b : qit_vector (5 DOWNTO 0) := "001000";

CONSTANT b_input : qit_vector (5 DOWNTO 0) := "010000";

CONSTANT a_sub_b : qit_vector (5 DOWNTO 0) := "100000";

END alu_operations;

ENTITY arithmetic_logic_unit IS PORT (a_side, b_side : IN byte;

alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub : IN qit; in_flags : IN nibble; z_out : OUT byte; out_flags : OUT nibble);END arithmetic_logic_unit;--ARCHITECTURE behavioral OF arithmetic_logic_unit IS

BEGIN

coding: PROCESS (a_side, b_side, alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub)

VARIABLE t : qit_vector (9 DOWNTO 0);

VARIABLE v, c, z, n : qit;

ALIAS n_flag_in : qit IS in_flags(0);

ALIAS z_flag_in : qit IS in_flags(1);

ALIAS c_flag_in : qit IS in_flags(2);

ALIAS v_flag_in : qit IS in_flags(3);

BEGIN

CASE qit_vector (5 DOWNTO 0)’ (alu_sub, alu_b, alu_add, alu_a, alu_not, alu_and) IS

WHEN a_add_b =>

t := add_cv (b_side, a_side, c_flag_in);

c := t(8); v := t(9); -- other flags are set at the end

WHEN a_sub_b =>

t := sub_cv (b_side, a_side, c_flag_in);

c := t(8); v := t(9);

WHEN a_and_b =>

t (7 DOWNTO 0) := a_side AND b_side;

c := c_flag_in; v := v_flag_in;

WHEN a_input =>

t (7 DOWNTO 0) := a_side;

c := c_flag_in; v := v_flag_in;

WHEN b_input =>

t (7 DOWNTO 0) := b_side;

c := c_flag_in; v := v_flag_in;

WHEN b_compl =>

t (7 DOWNTO 0) := NOT b_side;

c := c_flag_in; v := v_flag_in;

WHEN OTHERS => NULL;

END CASE;

n := t(7);

z := set_if_zero (t (7 DOWNTO 0));

z_out <= t (7 DOWNTO 0);

out_flags <= (v, c, z, n);

END PROCESS coding;

END behavioral;

Parwan shu. (a) Logic symbol, (b) one bit hardware.

ENTITY shifter_unit IS PORT (alu_side : IN byte; arith_shift_left, arith_shift_right : IN qit; in_flags : IN nibble; obus_side : OUT byte; out_flags : OUT nibble);

END shifter_unit;

--

ARCHITECTURE behavioral OF shifter_unit IS

BEGIN

coding: PROCESS (alu_side, arith_shift_left, arith_shift_right)

VARIABLE t : qit_vector (7 DOWNTO 0);

VARIABLE v, c, z, n : qit;

ALIAS n_flag_in : qit IS in_flags(0);

ALIAS z_flag_in : qit IS in_flags(1);

ALIAS c_flag_in : qit IS in_flags(2);

ALIAS v_flag_in : qit IS in_flags(3);

BEGIN

IF arith_shift_right = '0' AND arith_shift_left = '0' THEN

t := alu_side (7 DOWNTO 0);

(v, c, z, n) := in_flags; ELSIF arith_shift_left = '1' THEN t := alu_side (6 DOWNTO 0) & '0'; n := t (7); z := set_if_zero (t);

c := alu_side (7);

v := alu_side (6) XOR alu_side (7);

ELSIF arith_shift_right = '1' THEN

t := alu_side (7) & alu_side (7 DOWNTO 1);

n := t (7);

z := set_if_zero (t);

c := c_flag_in;

v := v_flag_in;

END IF;

obus_side <= t;

out_flags <= (v, c, z, n);

END PROCESS coding;

END behavioral;

The status register. (a) Logic symbol, (b) one bit hardware.

ENTITY status_register_unit IS PORT (in_flags : IN nibble; out_status : OUT nibble; load, cm_carry, ck : IN qit );END status_register_unit;

--

ARCHITECTURE behavioral OF status_register_unit IS

BEGIN

PROCESS (ck)

VARIABLE internal_state : nibble := "0000";

ALIAS internal_c : qit IS internal_state (2);

BEGIN

IF (ck = '0') THEN

IF (load = '1') THEN

internal_state := in_flags;

ELSIF (cm_carry = '1') THEN

internal_c := NOT internal_c;

END IF;

out_status <= internal_state;

END IF;

END PROCESS;

END behavioral;

ENTITY accumulator_unit IS PORT (i8 : IN byte; o8 : OUT byte; load, zero, ck : IN qit);

END accumulator_unit;

--

ARCHITECTURE dataflow OF accumulator_unit IS

BEGIN

enable : BLOCK (load = '1')

BEGIN

clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD )

BEGIN

o8 <= GUARDED "00000000" WHEN zero = '1' ELSE i8;

END BLOCK clocking;

END BLOCK enable;

END dataflow;

The Parwan instruction, (a) Logic symbol, (b) one bit hardware.

ENTITY instruction_register_unit IS

PORT (i8 : IN byte; o8 : OUT byte; load, ck : IN qit);

END instruction_register_unit;

--

ARCHITECTURE dataflow OF instruction_register_unit IS

BEGIN

enable : BLOCK (load = '1')

BEGIN

clocking : BLOCK ( (ck = '0' AND NOT ck'STABLE) AND GUARD )

BEGIN

o8 <= GUARDED i8;

END BLOCK clocking;

END BLOCK enable;

END dataflow;

Parwan program counter, (a) Logic symbol, (b) one bit hardware.

ENTITY program_counter_unit IS

PORT (i12 : IN twelve; o12 : OUT twelve;

increment, load_page, load_offset, reset, ck : IN qit);

END program_counter_unit;

--

ARCHITECTURE behavioral OF program_counter_unit IS

BEGIN

PROCESS (ck)

VARIABLE internal_state : twelve := zero_12;

BEGIN

IF (ck = '0' ) THEN

IF reset = '1' THEN

internal_state := zero_12;

ELSIF increment = '1' THEN

internal_state := inc (internal_state);

ELSE

IF load_page = '1' THEN

internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8);

END IF;

IF load_offset = '1' THEN

internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0);

END IF;

END IF;

o12 <= internal_state;

END IF;

END PROCESS;

END behavioral;

Logic symbol for the memory address register of Parwan.

ENTITY memory_address_register_unit IS

PORT (i12 : IN twelve; o12 : OUT twelve;

load_page, load_offset, ck : IN qit);

END memory_address_register_unit;

--

ARCHITECTURE behavioral OF memory_address_register_unit IS

BEGIN

PROCESS (ck)

VARIABLE internal_state : twelve := zero_12;

BEGIN

IF (ck = '0' ) THEN

IF load_page = '1' THEN

internal_state (11 DOWNTO 8) := i12 (11 DOWNTO 8);

END IF;

IF load_offset = '1' THEN

internal_state (7 DOWNTO 0) := i12 (7 DOWNTO 0);

END IF;

o12 <= internal_state;

END IF;

END PROCESS;

END behavioral;

ENTITY par_data_path IS

PORT (databus : INOUT wired_byte BUS := "ZZZZZZZZ"; adbus : OUT twelve;

clk : IN qit;

-- register controls:

load_ac, zero_ac,

load_ir,

increment_pc, load_page_pc, load_offset_pc, reset_pc,

load_page_mar, load_offset_mar,

load_sr, cm_carry_sr,

-- bus connections:

pc_on_mar_page_bus, ir_on_mar_page_bus,

pc_on_mar_offset_bus, dbus_on_mar_offset_bus,

pc_offset_on_dbus, obus_on_dbus, databus_on_dbus,

mar_on_adbus,

dbus_on_databus,

-- logic unit function control inputs:

arith_shift_left, arith_shift_right,

alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub : IN qit;

-- outputs to the controller:

ir_lines : OUT byte; status : OUT nibble

);

END par_data_path;

ARCHITECTURE structural OF par_data_path IS

--

COMPONENT ac

PORT (i8: IN byte; o8: OUT byte; load, zero, ck: IN qit);

END COMPONENT;

FOR r1: ac USE ENTITY WORK.accumulator_unit (dataflow);

--

COMPONENT ir

PORT (i8: IN byte; o8: OUT byte; load, ck: IN qit);

END COMPONENT;

FOR r2: ir USE ENTITY WORK.instruction_register_unit (dataflow);

--

COMPONENT pc

PORT (i12 : IN twelve; o12 : OUT twelve;

increment, load_page, load_offset, reset, ck : IN qit);

END COMPONENT;

FOR r3: pc USE ENTITY WORK.program_counter_unit (behavioral);

--

COMPONENT mar

PORT (i12 : IN twelve; o12 : OUT twelve; load_page, load_offset, ck : IN qit);

END COMPONENT;

FOR r4: mar USE ENTITY WORK.memory_address_register_unit (behavioral);

--

COMPONENT sr

PORT (in_flags : IN nibble; out_status : OUT nibble; load, cm_carry, ck : IN qit );

END COMPONENT;

FOR r5 : sr USE ENTITY WORK.status_register_unit (behavioral);

--

COMPONENT alu

PORT (a_side, b_side : IN byte; alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub : IN qit;

in_flags : IN nibble; z_out : OUT byte; out_flags : OUT nibble);

END COMPONENT;

FOR l1 : alu USE ENTITY WORK.arithmetic_logic_unit (behavioral);

--

COMPONENT shu

PORT (alu_side : IN byte; arith_shift_left, arith_shift_right : IN qit;

in_flags : IN nibble; obus_side : OUT byte; out_flags : OUT nibble);

END COMPONENT;

FOR l2 : shu USE ENTITY WORK.shifter_unit (behavioral);

--

SIGNAL ac_out, ir_out, alu_out, obus : byte;

SIGNAL alu_a_inp : byte;

SIGNAL pc_out, mar_out : twelve;

SIGNAL dbus : wired_byte BUS;

SIGNAL alu_flags, shu_flags, sr_out : nibble;

SIGNAL mar_bus : wired_twelve BUS;

SIGNAL mar_inp : twelve;

BEGIN

-- bus connections --

--

dbus1: alu_a_inp <= qit_vector (dbus);

dbus2: BLOCK (dbus_on_mar_offset_bus = '1')

BEGIN

mar_bus (7 DOWNTO 0) <= GUARDED dbus;

END BLOCK dbus2;

dbus3: BLOCK (dbus_on_databus = '1')

BEGIN

databus <= GUARDED dbus;

END BLOCK dbus3;

--

obus1: BLOCK (obus_on_dbus = '1')

BEGIN

dbus <= GUARDED wired_qit_vector (obus);

END BLOCK obus1;

--

databus1: BLOCK (databus_on_dbus = '1')

BEGIN

dbus <= GUARDED databus;

END BLOCK databus1;

--

mar_bus1: mar_inp <= qit_vector (mar_bus);

--

-- register connections --

--

r1: ac PORT MAP (obus, ac_out, load_ac, zero_ac, clk);

--

r2: ir PORT MAP (obus, ir_out, load_ir, clk);

ir1: ir_lines <= ir_out;

ir2: BLOCK (ir_on_mar_page_bus = '1')

BEGIN

mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (ir_out (3 DOWNTO 0));

END BLOCK ir2;

r3: pc PORT MAP (mar_out, pc_out, increment_pc, load_page_pc, load_offset_pc, reset_pc, clk);

pc1: BLOCK (pc_on_mar_page_bus = '1')

BEGIN

mar_bus (11 DOWNTO 8) <= GUARDED wired_qit_vector (pc_out (11 DOWNTO 8));

END BLOCK pc1;

pc2: BLOCK (pc_on_mar_offset_bus = '1')

BEGIN

mar_bus (7 DOWNTO 0) <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0));

END BLOCK pc2;

pc3: BLOCK (pc_offset_on_dbus = '1')

BEGIN

dbus <= GUARDED wired_qit_vector (pc_out (7 DOWNTO 0));

END BLOCK pc3;

--

r4: mar PORT MAP (mar_inp, mar_out, load_page_mar, load_offset_mar, clk);

mar1: BLOCK (mar_on_adbus = '1')

BEGIN

adbus <= GUARDED mar_out;

END BLOCK mar1;

--

r5: sr PORT MAP (shu_flags, sr_out, load_sr, cm_carry_sr, clk);

sr1: status <= sr_out;

--

-- connection of logical and register structures --

--

l1: alu PORT MAP (alu_a_inp, ac_out, alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub,

sr_out, alu_out, alu_flags);

l2: shu PORT MAP (alu_out, arith_shift_left, arith_shift_right, alu_flags, obus, shu_flags);

END structural;

Typical hardware surrounding a control flip-flop. The logic block in this figure is designated by a bubble.

Example for the structure of Parwan control section.

ENTITY par_control_unit IS

GENERIC (read_delay, write_delay : TIME := 3 NS);

PORT (clk : IN qit;

-- register control signals:

load_ac, zero_ac,

load_ir,

increment_pc, load_page_pc, load_offset_pc, reset_pc,

load_page_mar, load_offset_mar,

load_sr, cm_carry_sr,

-- bus connection control signals:

pc_on_mar_page_bus, ir_on_mar_page_bus,

pc_on_mar_offset_bus, dbus_on_mar_offset_bus,

pc_offset_on_dbus, obus_on_dbus, databus_on_dbus,

mar_on_adbus,

dbus_on_databus,

-- logic unit function control outputs:

arith_shift_left, arith_shift_right, alu_and, alu_not, alu_a, alu_add, alu_b, alu_sub :

OUT ored_qit BUS;

-- inputs from the data section:

ir_lines : IN byte; status : IN nibble;

-- memory control and other external signals:

read_mem, write_mem : OUT ored_qit BUS; interrupt : IN qit

);

END par_control_unit;

ARCHITECTURE dataflow OF par_control_unit IS

SIGNAL s : ored_qit_vector (9 DOWNTO 1) REGISTER := "000000001";

BEGIN

Declarative part of the par_control_unit dataflow architecture.

Assigning signals with implied oring, par_control_unit outputs.

END BLOCK s1;

State 1: starting a fetch, (a) VHDL code, (b) Hardware.

END BLOCK s2;

State 2: completing a fetch, (a) VHDL code, (b) Hardware.

s3: BLOCK (s(3) = '1')

END BLOCK s4;

State 4: completing address of full address instructions; branching for indirect, direct, jsr, and branch, (a) VHDL code, (b) Hardware.

END BLOCK s5;

State 5: taking care of indirect addressing.

State 6: reading the actual operand, and executing jmp, sta, lda, and, add, and sub instructions, (a) VHDL code, (b) Hardware.

State 7: writing return address of subroutine; making pc point to top of subroutine, (a) VHDL code, (b) Hardware.

END BLOCK s8;

State 8: incrementing pc to skip location reserved for return address, (a) VHDL code, (b) Hardware.

END BLOCK s9;

General outline of Parwan controller.

Entity declaration of the Parwan CPU for its dataflow description.

END dataflow;

The general outline of dataflow architectture of Parwan CPU.

ARCHITECTURE input_output OF parwan_tester IS

COMPONENT parwan PORT (clk : IN qit; interrupt : IN qit;

read_mem, write_mem : OUT qit;

databus : INOUT wired_byte BUS; adbus : OUT twelve );

END COMPONENT;

SIGNAL clock, interrupt, read, write : qit;

SIGNAL data : wired_byte := "ZZZZZZZZ";

SIGNAL address : twelve;

TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF byte;

BEGIN

int : interrupt <= '1', '0' AFTER 4500 NS;

clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 140 US ELSE clock;

cpu : parwan PORT MAP (clock, interrupt, read, write, data, address);

mem : PROCESS

VARIABLE memory : byte_memory ( 0 TO 63 ) :=

("00000000", "00011000", "10100000", "00011001", --lda 24, sta 25

"00100000", "00011010", "01000000", "00011011", --and 26, add 27

"11100010", "11101001", "01100000", "00011100", --cac, asr, sub 28

"00010000", "00011101", "11000000", "00100100", --lda i 29, jsr 36

"11101000", "11100000", "10000000", "00100000", --asl, nop, jmp 32

"00000000", "00000000", "00000000", "00000000",

"01011100", "00000000", "01110000", "00010010", --(24, 25, 26, 27)

"00001100", "00011111", "00000000", "01011010", --(28, 29, 30, 31)

"10000000", "00010010", "00000000", "00000000", --jmp 18

"00000000", "11100010", "10010000", "00100100", -- , cma, jmp i 36

OTHERS => (OTHERS => ‘0’));

VARIABLE ia : INTEGER;

BEGIN

WAIT ON read, write;

qit2int (address, ia);

IF read = '1' THEN

IF ia >= 64 THEN

data <= "ZZZZZZZZ";

ELSE

data <= wired_byte ( memory (ia) );

END IF;

WAIT UNTIL read = '0';

data <= "ZZZZZZZZ";

ELSIF write = '1' THEN

IF ia < 64 THEN

memory (ia) := byte ( data );

END IF;

WAIT UNTIL write = '0';

END IF;

END PROCESS mem;

END input_output;

A simple test bench for Parwan behavioral and dataflow descriptions.

CONFIGURATION behavior OF parwan_tester IS

FOR input_output

FOR cpu : parwan

USE ENTITY behavioral.par_central_processing_unit(behavioral);

END FOR;

END FOR;

END behavior;

(a)

CONFIGURATION dataflow OF parwan_tester IS

FOR input_output

FOR cpu : parwan

USE ENTITY par_dataflow.par_central_processing_unit(dataflow);

END FOR;

END FOR;

END dataflow;

(b)

Configuring input_output architecture of Parwan tester (a) for testing behavioral architecture of par_central_processing_unit, (b) for testing dataflow architecture of par_central_processing_unit.

WHEN instr_fetch => ---------------------------------------2

-- read memory into ir

mar_on_adbus <= '1';

databus_on_dbus <= '1';

alu_a <= ‘1’;

load_ir <= '1';

increment_pc <= '1';

next_state <= do_one_bytes;

ELSE

next_state <= instr_fetch;

END IF;

ELSE

next_state <= instr_fetch;

END IF;

WHEN do_one_bytes => --------------------------------------3

. . .

Memory and bus signaling for fetch state of controller.