NORTHEASTERN UNIVERSITY
Electrical and Computer Engineering Department
Digital Systems Design With VHDL, Test # 2
ECE 3401 / DS 765F
Summer Quarter 1997
Week of Lecture 20
Computer Account #___________________
First Name :_________________________
Last Name :__________________________
Number :_____________________________
Signature :__________________________
Grade:
Problem 1. ______/25
Problem 2. ______/25
Problem 3. ______/25
Problem 4. ______/25
Total: ______/100
EXTRA SHEETS WILL NOT BE ACCEPTED
THIS IS A OPEN BOOK OPEN NOTE EXAM
YOU MUST SHOW COMPLETE WORK ON ALL PROBLEMS
YOU HAVE EXACTLY TWO HOURS FOR WORKING ON THIS TEST
1. Using the following package that uses the std_logic package, two architectures for the bussing entity are written. The threestate uses resolved signals and the processing architecture does not. Based on the behavior of the threestate architecture, fill in the blanks for the z_side output value in the processing architecture.
LIBRARY IEEE;
USE IEEE.std_logic_1164.std_ulogic;
--
PACKAGE class_test_test IS
SUBTYPE mvl4 IS std_ulogic RANGE '0' TO 'W'; --('0', '1', 'Z', 'X');
TYPE mvl4_2d IS ARRAY (mvl4, mvl4) OF mvl4;
TYPE mvl4_vector IS ARRAY (NATURAL RANGE <>) OF mvl4;
FUNCTION wire (a, b : mvl4) RETURN mvl4;
FUNCTION wiring ( drivers : mvl4_vector) RETURN mvl4;
SUBTYPE wired_mvl4 IS wiring mvl4;
TYPE wired_mvl4_vector IS ARRAY (NATURAL RANGE <>) OF wired_mvl4;
END class_test_test;
PACKAGE BODY class_test_test IS
FUNCTION wire (a, b : mvl4) RETURN mvl4 IS
CONSTANT mvl4_wire_table : mvl4_2d := (
('0','W','0','W'),
('W','1','1','W'),
('0','1','Z','W'),
('W','W','W','W'));
BEGIN
RETURN mvl4_wire_table (a, b);
END wire;
FUNCTION wiring ( drivers : mvl4_vector) RETURN mvl4 IS
VARIABLE accumulate : mvl4 := 'Z';
BEGIN
FOR i IN drivers'RANGE LOOP
accumulate := wire (accumulate, drivers(i));
END LOOP;
RETURN accumulate;
END wiring;
END class_test_test;
--
USE WORK.class_test_test.ALL;
ENTITY bussing IS
PORT (a_side, b_side : IN wired_mvl4_vector (3 DOWNTO 0);
a_select, b_select : IN mvl4;
z_side : OUT wired_mvl4_vector (3 DOWNTO 0));
END bussing;
--
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.std_ulogic;
USE IEEE.std_logic_1164."=";
--
USE WORK.class_test_test.ALL;
--
ARCHITECTURE threestate OF bussing IS
BEGIN
z_side <= a_side WHEN a_select = '1' ELSE "ZZZZ";
z_side <= b_side WHEN b_select = '1' ELSE "ZZZZ";
END threestate;
LIBRARY IEEE;
USE IEEE.std_logic_1164.std_ulogic;
USE IEEE.std_logic_1164."=";
--
USE WORK.class_test_test.ALL;
--
ARCHITECTURE processing OF bussing IS
BEGIN
PROCESS (a_side, b_side, a_select, b_select)
BEGIN
FOR i IN a_side'RANGE LOOP
IF a_select = '0' AND b_select = '0' THEN
z_side (i) <= ……;
ELSIF a_select = '1' AND b_select = '0' THEN
z_side (i) <= ……;
ELSIF a_select = '0' AND b_select = '1' THEN
z_side (i) <= ……;
ELSIF a_select = '1' AND b_select = '1' THEN
IF a_side (i) = '0' AND b_side (i) = '0' THEN z_side (i) <= ……;
ELSIF a_side (i) = '0' AND b_side (i) = '1' THEN z_side (i) <= ……;
ELSIF a_side (i) = '0' AND b_side (i) = 'W' THEN z_side (i) <= ……;
ELSIF a_side (i) = '0' AND b_side (i) = 'Z' THEN z_side (i) <= ……;
ELSIF a_side (i) = '1' AND b_side (i) = '0' THEN z_side (i) <= ……;
ELSIF a_side (i) = '1' AND b_side (i) = '1' THEN z_side (i) <= ……;
ELSIF a_side (i) = '1' AND b_side (i) = 'W' THEN z_side (i) <= ……;
ELSIF a_side (i) = '1' AND b_side (i) = 'Z' THEN z_side (i) <= ……;
ELSIF a_side (i) = 'Z' AND b_side (i) = '0' THEN z_side (i) <= ……;
ELSIF a_side (i) = 'Z' AND b_side (i) = '1' THEN z_side (i) <= ……;
ELSIF a_side (i) = 'Z' AND b_side (i) = 'W' THEN z_side (i) <= ……;
ELSIF a_side (i) = 'Z' AND b_side (i) = 'Z' THEN z_side (i) <= ……;
ELSIF a_side (i) = 'W' AND b_side (i) = '0' THEN z_side (i) <= ……;
ELSIF a_side (i) = 'W' AND b_side (i) = '1' THEN z_side (i) <= ……;
ELSIF a_side (i) = 'W' AND b_side (i) = 'W' THEN z_side (i) <= ……;
ELSIF a_side (i) = 'W' AND b_side (i) = 'Z' THEN z_side (i) <= ……;
END IF;
ELSIF a_select = 'W' OR b_select = 'W' THEN
z_side (i) <= ……;
ELSIF a_select = '1' THEN
z_side (i) <= ……;
ELSIF b_select = '1' THEN
z_side (i) <= ……;
END IF;
END LOOP;
END PROCESS;
END processing;
--
2. Use guarded block statements and intermediate signals to duplicate results of the threestate architecture of Problem 1. Fill in the blanks in the following code.
LIBRARY IEEE;
USE IEEE.std_logic_1164."=";
USE IEEE.std_logic_1164.std_ulogic;
--
USE WORK.class_test_test.ALL;
--
ARCHITECTURE blocking OF bussing IS
SIGNAL . . .
BEGIN
a: BLOCK (a_select = '1')
BEGIN
. . .
END BLOCK;
b: BLOCK (b_select = '1')
BEGIN
. . .
END BLOCK;
. . .
END blocking;
--
3. Given the following state machine description, 1) Show the state diagram this description is implementing. 2) Fill in the simulation result listing, note that there are simultaneous changes. 3) Add an asynchronous reset to this description.
ENTITY mooreb IS
PORT (data, clock : IN BIT; outz, waiting : OUT BIT); END mooreb;
--
ARCHITECTURE synthesizable OF mooreb IS
TYPE state IS (aa, bb, cc, dd);
SIGNAL nxt, present : state;
BEGIN
reg : PROCESS (clock)
BEGIN
IF (clock'EVENT AND clock = '1') THEN
present <= nxt;
END IF;
END PROCESS;
--
logic : PROCESS (present, data)
BEGIN
outz <= '0';
waiting <= '0';
CASE present IS
WHEN aa =>
IF data = '0' THEN nxt <= aa; ELSE nxt <= bb; END IF;
WHEN bb =>
IF data = '0' THEN nxt <= cc; ELSE nxt <= bb; END IF;
WHEN cc =>
IF data = '0' THEN nxt <= aa; ELSE nxt <= dd; END IF;
WHEN dd =>
IF data = '0' THEN nxt <= cc; ELSE nxt <= bb; END IF;
END CASE;
IF present = dd THEN outz <= '1'; END IF;
IF present = aa THEN waiting <= '1'; END IF;
END PROCESS;
END synthesizable;
|
ps |
delta |
data |
clock |
outz |
waiting |
|
0 |
+0 |
0 |
0 |
||
|
0 |
+1 |
0 |
0 |
||
|
30000 |
+0 |
1 |
0 |
||
|
40000 |
+0 |
1 |
1 |
||
|
40000 |
+2 |
1 |
1 |
||
|
65000 |
+0 |
0 |
1 |
||
|
75000 |
+0 |
0 |
0 |
||
|
120000 |
+0 |
0 |
1 |
||
|
125000 |
+0 |
1 |
1 |
||
|
155000 |
+0 |
0 |
0 |
||
|
180000 |
+0 |
1 |
0 |
||
|
200000 |
+0 |
1 |
1 |
||
|
200000 |
+2 |
1 |
1 |
||
|
215000 |
+0 |
0 |
1 |
||
|
235000 |
+0 |
0 |
0 |
||
|
275000 |
+0 |
1 |
0 |
||
|
280000 |
+0 |
1 |
1 |
||
|
280000 |
+2 |
1 |
1 |
||
|
305000 |
+0 |
0 |
1 |
||
|
315000 |
+0 |
0 |
0 |
||
|
330000 |
+0 |
1 |
0 |
||
|
360000 |
+0 |
1 |
1 |
||
|
365000 |
+0 |
0 |
1 |
||
|
395000 |
+0 |
0 |
0 |
||
|
425000 |
+0 |
1 |
0 |
||
|
440000 |
+0 |
1 |
1 |
||
|
455000 |
+0 |
0 |
1 |
||
|
475000 |
+0 |
0 |
0 |
||
|
480000 |
+0 |
1 |
0 |
||
|
515000 |
+0 |
0 |
0 |
||
|
520000 |
+0 |
0 |
1 |
||
|
555000 |
+0 |
0 |
0 |
||
|
575000 |
+0 |
1 |
0 |
||
|
600000 |
+0 |
1 |
1 |
||
|
600000 |
+2 |
1 |
1 |
||
|
605000 |
+0 |
0 |
1 |
||
|
630000 |
+0 |
1 |
1 |
||
|
635000 |
+0 |
1 |
0 |
||
|
665000 |
+0 |
0 |
0 |
||
|
680000 |
+0 |
0 |
1 |
||
|
680000 |
+2 |
0 |
1 |
||
|
715000 |
+0 |
0 |
0 |
||
|
725000 |
+0 |
1 |
0 |
||
|
755000 |
+0 |
0 |
0 |
||
|
760000 |
+0 |
0 |
1 |
||
|
760000 |
+2 |
0 |
1 |
||
|
780000 |
+0 |
1 |
1 |
||
|
795000 |
+0 |
1 |
0 |
||
|
815000 |
+0 |
0 |
0 |
||
|
840000 |
+0 |
0 |
1 |
||
|
875000 |
+0 |
1 |
0 |
||
|
905000 |
+0 |
0 |
0 |
||
|
920000 |
+0 |
0 |
1 |
||
|
930000 |
+0 |
1 |
1 |
||
|
955000 |
+0 |
1 |
0 |
||
|
965000 |
+0 |
0 |
0 |
||
|
1000000 |
+0 |
0 |
1 |
||
|
1025000 |
+0 |
1 |
1 |
||
|
1035000 |
+0 |
1 |
0 |
||
|
1055000 |
+0 |
0 |
0 |
||
|
1080000 |
+0 |
1 |
1 |
||
|
1115000 |
+0 |
0 |
0 |
||
|
1160000 |
+0 |
0 |
1 |
||
|
1175000 |
+0 |
1 |
1 |
||
|
1195000 |
+0 |
1 |
0 |
||
|
1205000 |
+0 |
0 |
0 |
||
|
1230000 |
+0 |
1 |
0 |
||
|
1240000 |
+0 |
1 |
1 |
||
|
1240000 |
+2 |
1 |
1 |
||
|
1265000 |
+0 |
0 |
1 |
||
|
1275000 |
+0 |
0 |
0 |
||
|
1320000 |
+0 |
0 |
1 |
||
|
1325000 |
+0 |
1 |
1 |
||
|
1355000 |
+0 |
0 |
0 |
||
|
1380000 |
+0 |
1 |
0 |
||
|
1400000 |
+0 |
1 |
1 |
||
|
1400000 |
+2 |
1 |
1 |
4. Parwan datapath is shown below. Make modifications for this processor to be able to perform full indirect addressing. Note that the present architecture only allows full indirect addresses to receive offset address of the operand. The new architecture should be able to read page and offset of the operand. Show dataflow VHDL code for the control steps that have to be added for this purpose.