ENTITY assign IS

PORT (enable : IN BIT; wave : OUT BIT);

END assign;

--

ARCHITECTURE one_process OF assign IS

BEGIN

PROCESS (enable)

BEGIN

wave <= '1', '0' AFTER 40 NS, '1' AFTER 80 NS;

END PROCESS;

END one_process;

--

ARCHITECTURE concurrent OF assign IS

SIGNAL rl : BIT; -- To use on right and left

BEGIN

rl <= '1', '0' AFTER 40 NS, '1' AFTER 80 NS WHEN enable'EVENT ELSE rl;

wave <= rl;

END concurrent;

--

ENTITY assign_tester IS END assign_tester;

--

ARCHITECTURE generation OF assign_tester IS

COMPONENT assign

PORT (enable : IN BIT; wave : OUT BIT);

END COMPONENT;

FOR a1 : assign USE ENTITY WORK.assign (one_process);

FOR a2 : assign USE ENTITY WORK.assign (concurrent);

SIGNAL enable, wave1, wave2 : BIT := '0';

BEGIN

a1 : assign PORT MAP (enable, wave1);

a2 : assign PORT MAP (enable, wave2);

enable <= '0', '1' AFTER 80 NS, '0' AFTER 110 NS, '1' AFTER 175 NS;

END generation;

The following code places sequential transactions on the drivers of isa, idb, tsa, and tdb signals. For each signal write a single concurrent signal assignment to place the same transactions on the driver the signal. In addition to four signal assignment for isa, idb, tsa, and tdb, you can use an activation signal and another signal assignment for activating it. Note: mvl3 is a 3-value logic defined to have ‘0’, ‘1’, ‘Z’ as its enumaration elements.

ENTITY sequential_transactions IS

PORT (isa, isb, ida, idb, tsa, tsb, tda, tdb : OUT mvl3 := 'Z' );

END sequential_transactions;

--

ARCHITECTURE in_process OF sequential_transactions IS

BEGIN

PROCESS

BEGIN

-- ('0', 15 NS) existing transaction

isa <= '0' AFTER 15 NS;

idb <= '0' AFTER 15 NS;

tsa <= '0' AFTER 15 NS;

tdb <= '0' AFTER 15 NS;

-- an incoming new transaction

isa <= '0' AFTER 20 NS;

idb <= '1' AFTER 10 NS;

tsa <= TRANSPORT '0' AFTER 20 NS;

tdb <= TRANSPORT '1' AFTER 10 NS;

WAIT;

END PROCESS;

END in_process;

--

USE WORK.values.ALL;

--

ARCHITECTURE activation OF sequential_transactions IS

SIGNAL a : mvl3 := '0';

BEGIN

a <= '1';

--

isa <= '0' AFTER 15 NS WHEN a = '0' ELSE '0' AFTER 20 NS;

tsa <= '0' AFTER 15 NS, '0' AFTER 20 NS;

idb <= '0' AFTER 15 NS WHEN a = '0' ELSE '1' AFTER 10 NS;

tdb <= TRANSPORT '0' AFTER 15 NS WHEN a = '0' ELSE '1' AFTER 10 NS;

END activation;

--

--

A signal driver is passed to a procedure when SIGNAL is declared with a procedure parameter, otherwise signal value is passed to the procedure. Considering this, show wave forms generated on see_flag and look_flag from time 0 to the time that no more events occur in the circuit.

ENTITY drivpass IS

PORT (see_flag, look_flag : OUT BIT);

PROCEDURE wait_and_look (SIGNAL passed : IN BIT; SIGNAL flag : OUT BIT) IS

BEGIN

WAIT FOR 15 NS;

flag <= passed;

END wait_and_look;

PROCEDURE wait_and_see (passed : IN BIT; SIGNAL flag : OUT BIT) IS

BEGIN

WAIT FOR 15 NS;

flag <= passed;

END wait_and_see;

END drivpass;

--

ARCHITECTURE concurrent OF drivpass IS

SIGNAL future_look : BIT := '0';

BEGIN

future_look <= '1' AFTER 10 NS, '0' AFTER 20 NS,

'1' AFTER 40 NS, '0' AFTER 60 NS,

'1' AFTER 70 NS;

wait_and_see (future_look, see_flag);

wait_and_look (future_look, look_flag);

END concurrent;

4. Is the statement shown in the statement part of the architecture shown below a valid VHDL statement? Does this architercure simulate as it is shown here? If not, write a function so that when used by the description shown here, the signal assignment in this description becomes a valid simulatable VHDL statement. What you write the function to do is not important, just write a valid function to return any thing that makes the statement simulatable.

ENTITY whatisthis IS

FUNCTION "<=" (w : BOOLEAN; x : INTEGER) RETURN INTEGER IS

BEGIN

IF w = FALSE AND x >= 0 THEN

RETURN +1;

ELSE

RETURN -1;

END IF;

END "<=";

END whatisthis;

--

ARCHITECTURE behavioral OF whatisthis IS

SIGNAL a, b, c, d : INTEGER := 0;

BEGIN

a <= (b <= c) <= d;

END behavioral;

Write a VHDL architecture with an enable input and 3 data inputs a, b, and c. When enable becomes ‘1’, events on a, b, and c are counted and will be reported to the output when enable becomes 0. The output is a 4-bit binary number that can only keep modulo-16 counts of the input events. Consider simultanious events on the inputs.

ENTITY signalat IS

PORT (start, a, b, c : IN BIT; events : OUT BIT_VECTOR);

PROCEDURE int2bin (int : IN INTEGER; SIGNAL bin : OUT BIT_VECTOR) IS

VARIABLE tmp : INTEGER;

BEGIN

tmp := int;

FOR i IN 0 TO (bin'LENGTH - 1) LOOP

IF (tmp MOD 2 = 1) THEN

bin (i) <= '1';

ELSE bin (i) <= '0';

END IF;

tmp := tmp / 2;

END LOOP;

END int2bin;

END signalat;

--

ARCHITECTURE procedural OF signalat IS

PROCEDURE see_events (SIGNAL start, a, b, c : IN BIT;

SIGNAL events : OUT BIT_VECTOR) IS

VARIABLE count : INTEGER := 0;

BEGIN

IF start'EVENT and start = '1' THEN

LOOP

IF a'EVENT THEN

count := count + 1;

int2bin (count, events);

END IF;

IF b'EVENT THEN

count := count + 1;

int2bin (count, events);

END IF;

IF c'EVENT THEN

count := count + 1;

int2bin (count, events);

END IF;

WAIT ON a, b, c;

EXIT WHEN start'EVENT;

END LOOP;

END IF;

END see_events;

BEGIN

see_events (start, a, b, c, events);

END procedural;

ARCHITECTURE processing OF signalat IS

BEGIN

see_events: PROCESS (a, b, c, start)

VARIABLE count : INTEGER := 0;

BEGIN

IF start'EVENT and start = '1' THEN

count := 0;

END IF;

IF start = '1' AND a'EVENT THEN

count := count + 1;

END IF;

IF start = '1' AND b'EVENT THEN

count := count + 1;

END IF;

IF start = '1' AND c'EVENT THEN

count := count + 1;

END IF;

IF start = '0' AND start'EVENT THEN

int2bin (count, events);

END IF;

END PROCESS;

END processing;

Write a dataflow description using concurrent signals assignments for an unconstrained counter that starts in 00…001 state and with each clock, it rotates with the most significant bit receiving the complement of the least significant bit. For example if the current contentc are 1001101 the next two counts will be 0100110 and 1010011.