PART 8

Behavioral_Synthesis

Synthesis style

- Description style
- Hardware style
- Coding style

Necessary Package
Interface
General Layout
Registers
Clocking
Sequencing
Simulation and Synthesis

Behavioral_synthesis.style

Description style:
- State diagram style
- Program for each state

Programs specify register transfers and arithmetic
Bussing will be decided by synthesis tool
Each program is sequential
Can use a state diagram template
Customize each state program

Behavioral_synthesis.style

Generated hardware contains a logical unit and an array of registers

State register is handled like any other register

Clocking influences registers only

Number of states depends on state assignment

Behavioral_synthesis.style

ARCHITECTURE synthesizable ...
state and register
declarations
BEGIN
clocking : PROCESS ( clk, ... )
BEGIN
clocked next to present transfers
for registers and states
END PROCESS, clocking;
- -
sequencing : PROCESS ( all present values and inputs )
BEGIN
assigning combinational values
setting present values with next
CASE present_state IS
WHEN state_i =>
sequential program i
conditionally set next values
use present values for conditions
conditionally set next state
WHEN state_j =>
...
END CASE
END PROCESS;
END synthesizable;

In declarations, next and present signals are declared for all registers

Clocking process uses clock to transfer next to present values

Sequencing process contains sequential programs for each state

Behavioral_synthesis.parwan.packages

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
PACKAGE synthesis_parameters IS
CONSTANT single_byte_instructions : std_logic_vector (3 DOWNTO 0) := "1110";
CONSTANT cla : std_logic_vector (3 DOWNTO 0) := "0001";
CONSTANT cma : std_logic_vector (3 DOWNTO 0) := "0010";
CONSTANT cmc : std_logic_vector (3 DOWNTO 0) := "0100";
CONSTANT asl : std_logic_vector (3 DOWNTO 0) := "1000";
CONSTANT asr : std_logic_vector (3 DOWNTO 0) := "1001";
CONSTANT jsr : std_logic_vector (2 DOWNTO 0) := "110";
CONSTANT bra : std_logic_vector (3 DOWNTO 0) := "1111";
CONSTANT indirect : std_logic := '1';
CONSTANT jmp : std_logic_vector (2 DOWNTO 0) := "100";
CONSTANT sta : std_logic_vector (2 DOWNTO 0) := "101";
CONSTANT lda : std_logic_vector (2 DOWNTO 0) := "000";
CONSTANT ann : std_logic_vector (2 DOWNTO 0) := "001";
CONSTANT add : std_logic_vector (2 DOWNTO 0) := "010";
CONSTANT sbb : std_logic_vector (2 DOWNTO 0) := "011";
CONSTANT jsr_or_bra : std_logic_vector (1 DOWNTO 0) := "11";
--
CONSTANT zero_12 : std_logic_vector (11 DOWNTO 0) := "000000000000";
CONSTANT zero_8 : std_logic_vector (7 DOWNTO 0) := "00000000";
END synthesis_parameters;

Parwan synthesizable description uses synthesizable_package

Constants used for readability of code

Use the std_logic_1164 mvl9

Behavioral_synthesis.parwan.packages

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
PACKAGE synthesis_utilities IS
FUNCTION all_or (v : std_logic_vector) RETURN std_logic;
FUNCTION addsub_cv (a, b : std_logic_vector; cin : std_logic; add_sub : std_logic)
RETURN std_logic_vector;
SUBTYPE nibble IS std_logic_vector (3 DOWNTO 0);
SUBTYPE byte IS std_logic_vector (7 DOWNTO 0);
SUBTYPE twelve IS std_logic_vector (11 DOWNTO 0);
END synthesis_utilities;
--

Parwan synthesizable_utilities include functions and type declarations

all_or and addsub_cv bodies are in the package body

Behavioral_synthesis.parwan.packages

FUNCTION all_or (v : std_logic_vector) RETURN std_logic IS
VARIABLE temp : std_logic;
BEGIN
temp := '0';
FOR i IN v'RANGE LOOP
temp := temp OR v(i);
END LOOP;
RETURN temp;
END all_or;

all_or ORes all its input bits

Implies a multi_input OR gate

Used for checking zero result

Behavioral_synthesis.parwan.packages

FUNCTION addsub_cv
(a, b : std_logic_vector; cin : std_logic; add_sub : std_logic)
RETURN std_logic_vector IS
--for adding add_sub is 0, for subtracting add_sub is 1
--left bits of a and b are sign bit
VARIABLE r: std_logic_vector (a'LEFT + 2 DOWNTO 0); --temp result
-- Left two bits of r are for v and c respectively
VARIABLE c: std_logic_vector (a'LEFT DOWNTO 0); --intermediate carry
VARIABLE a_sign, b_sign: std_logic; --sign bits of a and b
VARIABLE cin_signed : std_logic; --complement cin for sub
VARIABLE b_signed : std_logic_vector (b'RANGE); --complement b for sub
BEGIN
cin_signed := cin XOR add_sub;
FOR i IN b'RANGE LOOP
b_signed (i) := b(i) XOR add_sub;
END LOOP;
a_sign := a(a'LEFT); b_sign := b_signed(b'LEFT);
r(0) := a(0) XOR b_signed(0) XOR cin_signed;
c(0) := ((a(0)XOR b_signed(0))AND cin_signed)OR (a(0) AND b_signed(0));
FOR i IN 1 TO (a'LEFT) LOOP
r(i) := a(i) XOR b_signed(i) XOR c(i-1);
c(i) := ((a(i) XOR b_signed(i)) AND c(i-1)) OR (a(i) AND b_signed(i));
END LOOP;
r(a'LEFT+1) := c(a'LEFT);
IF a_sign = b_sign AND r(a'LEFT) /= a_sign
THEN r(a'LEFT+2) := '1'; --overflow
ELSE r(a'LEFT+2) := '0'; END IF;
RETURN r;
END addsub_cv;
END synthesis_utilities;

addsub_cv adds or subtracts

MSB bits are v and c bits

Combined add_sub helps resource sharing

Behavioral_synthesis.parwan.interface

Interface and libraries for synthesizable Parwan

std_logic is resolved signal

databus is INOUT to be driver by the CPU or the memory

Behavioral_synthesis.parwan.general_layout

ARCHITECTURE behavioral_synthesizable

Declarations:
ac, ir, ..., states

BEGIN
Clocking process

Sequencing : PROCESS
CASE present_state
.
.
.
END CASE

END behavioral_synthesizable;

Declare registers and states

Update registers in clocking PROCESS

Condition on present_state perform register and arithmetic operations

Behavioral_synthesis.parwan.registers

SIGNAL ac, next_ac, ir, next_ir : std_logic_vector (7 DOWNTO 0);
SIGNAL sr, next_sr : std_logic_vector (3 DOWNTO 0);
SIGNAL pc, next_pc, mar, next_mar : std_logic_vector (11 DOWNTO 0);
TYPE cpu_states IS (initial, instr_fetch, do_one_bytes, opnd_fetch,
do_indirect, do_two_bytes, do_jsr, continue_jsr,
do_branch);
SIGNAL present_state, next_state : cpu_states;

Declarations include present & next for all registers and states

No buses are declared

There are 9 CPU states

Use CPU_states enumeration type for the states of Parwan

Behavioral_synthesis.parwan.clocking

clocking : PROCESS (clk, interrupt)
BEGIN
IF (interrupt = '1') THEN
present_state <= initial;
ac <= zero_8;
ir <= zero_8;
sr <= "0000";
pc <= zero_12;
mar <= zero_12;
ELSIF clk'EVENT AND clk = '0' THEN
ac <= next_ac;
ir <= next_ir;
sr <= next_sr;
pc <= next_pc;
mar <= next_mar;
present_state <= next_state;
END IF;
END PROCESS clocking;

Clock condition must be the last condition

Resetting is done synchronously

On falling edge of clock all next values are transferred to present