• Subprograms
  

Describing Logic

Aid in testing

Utilities

• Packaging
  

Components

Utilities

• Parametrization
  

Generic design

Generic specification

Using defaults

Using fixed values

Passing values

• Top level configuration
  

Comparator example

Register example

• Design libraries
  
• A complete example

a_gt_b = a. gt + b'. gt+ a.b'
a_eq_b = a.b.eq + a'.b'.eq
a_lt_b = b.lt + a'.lt + b.a'

ARCHITECTURE functional OF bit_comparator IS
FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS
BEGIN
RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x);
END fgl;
FUNCTION feq (w, x, eq : BIT) RETURN BIT IS
BEGIN
RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq);
END feq;
BEGIN
a_gt_b <= fgl (a, b, gt) AFTER 12 NS;
a_eq_b <= feq (a, b, eq) AFTER 12 NS;
a_lt_b <= fgl (b, a, lt) AFTER 12 NS;
END functional;

• Will begin with simple functions
  
• Functions are used to simplify descriptions
  
• Function definition can only be used by this architecture

Design_Organization.syntax

• Function is a subprogram
  
• Subprogram specification specifies function
  
• Inside a function is sequential

ARCHITECTURE structural OF nibble_comparator IS
COMPONENT comp1
PORT (a, b, gt, eq, lt : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
FOR ALL : comp1 USE ENTITY WORK.bit_comparator (functional);
CONSTANT n : INTEGER := 4;
SIGNAL im : BIT_VECTOR ( 0 TO (n-1)*3-1);
BEGIN
c_all: FOR i IN 0 TO n-1 GENERATE
l: IF i = 0 GENERATE
least: comp1 PORT MAP (a(i), b(i), gt, eq, lt, im(0), im(1), im(2) );
END GENERATE;
m: IF i = n-1 GENERATE
most: comp1 PORT MAP
(a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), a_gt_b, a_eq_b, a_lt_b);
END GENERATE;
r: IF i > 0 AND i < n-1 GENERATE
rest: comp1 PORT MAP
(a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0), im(i*3+1), im(i*3+2) );
END GENERATE;
END GENERATE;
END structural;

• A nibble comparator is based on our functional architecture
  
• Only bindings needs to be changed
  

Design_Organization.subprograms.aid_in_testing

• Declare an array of 13 integers
  
• A testbench for nibble comparator
  

Design_Organization.subprograms.Aid_intesting

• apply_data procedure uses integers and places binary equivalent on target
  
• Two concurrent procedure calls place data
  
• Body of procedure is sequential and sensitive to a / b
  
• Invoked at the initialization or when inputs change

Design_Organization.subprograms.aid_in_testing

• Use of function simplifies bit_comparator description
  
• Price paid is accuracy in simulation

Design_Organization.subprograms.syntax

• Subprogram specification can be procedure or function
  
• Body is sequential
  
• Procedure call can be sequential or concurrent
  

Design_Organization.subprograms.syntax

• Body of a subprogram contains sequential statements
  
• FOR is a sequential statement
  
• IF is a sequential statement
  

PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS
VARIABLE result: INTEGER;
BEGIN
result := 0;
FOR i IN 0 TO (bin'LENGTH - 1) LOOP
IF bin(i) = '1' THEN result := result + 2**i; END IF;
END LOOP;
int := result;
END bin2int;

PROCEDURE apply_data
(SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0);
CONSTANT values : IN integers; CONSTANT period : IN TIME) IS
VARIABLE buf : BIT_VECTOR (3 DOWNTO 0);
BEGIN
FOR i IN 0 TO 12 LOOP
int2bin (values(i), buf);
target <= TRANSPORT buf AFTER i * period;
END LOOP;
END apply_data;

PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS
VARIABLE tmp : INTEGER;
VARIABLE buf : BIT_VECTOR (bin'RANGE);
BEGIN
tmp := int;
FOR i IN 0 TO (bin'LENGTH - 1) LOOP
IF (tmp MOD 2 = 1) THEN bin (i) := '1'; ELSE bin (i) := '0'; END IF;
tmp := tmp / 2;
END LOOP;
END int2bin;

• Utilities include procedure for number conversion
  
• Use 'RANGE and 'LENGTH for more general procedures
  
• Use int2bin in apply_data
  

PACKAGE simple_gates IS
COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT;
COMPONENT n2 PORT (i1, i2: IN BIT; o1: OUT BIT); END COMPONENT;
COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT;
END simple_gates;

USE WORK.simple_gates.ALL;
ARCHITECTURE gate_level OF bit_comparator IS
FOR ALL : n1 USE ENTITY WORK.inv (single_delay);
FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay);
FOR ALL : n3 USE ENTITY WORK.nand3 (single_delay);
-- Intermediate signals
SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;
BEGIN
-- a_gt_b output
g0 : n1 PORT MAP (a, im1); g1 : n1 PORT MAP (b, im2);
g2 : n2 PORT MAP (a, im2, im3); g3 : n2 PORT MAP (a, gt, im4);
g4 : n2 PORT MAP (im2, gt, im5);
g5 : n3 PORT MAP (im3, im4, im5, a_gt_b);
-- a_eq_b output
g6 : n3 PORT MAP (im1, im2, eq, im6);
g7 : n3 PORT MAP (a, b, eq, im7);
g8 : n2 PORT MAP (im6, im7, a_eq_b);
-- a_lt_b output
g9 : n2 PORT MAP (im1, b, im8); g10 : n2 PORT MAP (im1, lt, im9);
g11 : n2 PORT MAP (b, lt, im10);
g12 : n3 PORT MAP (im8, im9, im10, a_lt_b);
END gate_level;

• Use component packages to avoid many declarations
  
• Architecture includes instantiations of package components
  

USE WORK.simple_gates.ALL

-- is equaivalent to:

USE
WORK.simple_gates.n1,
WORK.simple_gates.n2,
WORK.simple_gates.n3;
-- n1, n2 and n3 component declarations are visible

• Apply USE to make a package visible
  
• WORK is the library of the component package
  
• Both forms shown above are quaivalent

PACKAGE basic_utilities IS
TYPE integers IS ARRAY (0 TO 12) OF INTEGER;
FUNCTION fgl (w, x, gl : BIT) RETURN BIT;
FUNCTION feq (w, x, eq : BIT) RETURN BIT;
PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER);
PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR);
PROCEDURE apply_data (
SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0);
CONSTANT values : IN integers; CONSTANT period : IN TIME);
END basic_utilities;

PACKAGE BODY basic_utilities IS
FUNCTION fgl (w, x, gl : BIT) RETURN BIT IS
BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x);
END fgl;
FUNCTION feq (w, x, eq : BIT) RETURN BIT IS
BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq);
END feq;
PROCEDURE bin2int (bin : IN BIT_VECTOR; int : OUT INTEGER) IS
VARIABLE result: INTEGER;
BEGIN
result := 0;
FOR i IN 0 TO (bin'LENGTH - 1) LOOP
IF bin(i) = '1' THEN result := result + 2**i; END IF;
END LOOP;
int := result;
END bin2int;
PROCEDURE int2bin (int : IN INTEGER; bin : OUT BIT_VECTOR) IS
VARIABLE tmp : INTEGER;
BEGIN
tmp := int;
FOR i IN 0 TO (bin'LENGTH - 1) LOOP
IF (tmp MOD 2 = 1) THEN bin (i) := '1'; ELSE bin (i) := '0'; END IF;
tmp := tmp / 2;
END LOOP;
END int2bin;
PROCEDURE apply_data (
SIGNAL target : OUT BIT_VECTOR (3 DOWNTO 0);
CONSTANT values : IN integers; CONSTANT period : IN TIME) IS
VARIABLE buf : BIT_VECTOR (3 DOWNTO 0);
BEGIN
FOR i IN 0 TO 12 LOOP
int2bin (values(i), buf);
target <= TRANSPORT buf AFTER i * period;
END LOOP;
END apply_data;
END basic_utilities;

• Can package subprograms and types
  

Design_Organization.packaging.utilities

USE WORK.basic_utilities.ALL;
ARCHITECTURE procedural OF nibble_comparator_test_bench IS
COMPONENT comp4 PORT (
a, b : IN bit_vector (3 DOWNTO 0); gt, eq, lt : IN BIT;
a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
FOR a1 : comp4 USE ENTITY WORK.nibble_comparator(structural);
SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0);
SIGNAL eql, lss, gtr : BIT;
SIGNAL vdd : BIT := '1';
SIGNAL gnd : BIT := '0';
BEGIN
a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, lss);
apply_data (a, 00&15&15&14&14&14&14&10&00&15&00&00&15, 500 NS);
apply_data (b, 00&14&14&15&15&12&12&12&15&15&15&00&00, 500 NS);
END procedural;

• USE statement makes basic_utilities package visible
  
• Two examples are shown
  

USE WORK.basic_utilities.ALL;
USE WORK.basic_utilities .bin2int;
...

• Assumes basic_utilities is in the WORK library
  
• Only those in the package declaration become visible
  
• Can use individual procedures of type declarations

Design_Organization.parametrization

ENTITY nand2_t IS
GENERIC (tplh : TIME := 4 NS; tphl : TIME := 6 NS);
PORT (i1, i2 : IN BIT; o1 : OUT BIT);
END nand2_t;
--
ARCHITECTURE average_delay OF nand2_t IS
BEGIN
o1 <= i1 NAND i2 AFTER (tplh + tphl) / 2;
END average_delay;

ENTITY nand3_t IS
GENERIC (tplh : TIME := 5 NS; tphl : TIME := 7 NS);
PORT (i1, i2, i3 : IN BIT; o1 : OUT BIT);
END nand3_t;
--
ARCHITECTURE average_delay OF nand3_t IS
BEGIN
o1 <= NOT ( i1 AND i2 AND i3 ) AFTER (tplh + tphl) / 2;
END average_delay;

• Generics can pass design parameters
  
• New versions of gate descriptions contain timing generics
  
• Generics can include default values

Design_Organization.parametrization

• Component aspects help clarify interconnections
  
• Dotted lines are used for generics

Design_Organization.parametrization.syntax

• Generic clause has syntax similar to port clause
  
• Interface constant declaration

Design_Organization.parametrization

• There are many alternatives for passing values to generics
  
• Defining parameters by
  
• Using defaults
  
• Assigning fixed values
  
• Passing values from higher level components
  
• Configuring designs

Design_Organization.parametrization.default_values

• Component declarations do not contain generics
  
• Component instantiation are as before
  
• If default values exits, they are used
  

ARCHITECTURE fixed_delay OF bit_comparator IS
COMPONENT n1
GENERIC (tplh, tphl : TIME); PORT (i1: IN BIT; o1: OUT BIT);
END COMPONENT;
COMPONENT n2
GENERIC (tplh, tphl : TIME); PORT (i1, i2: IN BIT; o1: OUT BIT);
END COMPONENT;
COMPONENT n3
GENERIC (tplh, tphl : TIME); PORT (i1, i2, i3: IN BIT; o1: OUT BIT);
END COMPONENT;
FOR ALL : n1 USE ENTITY WORK.inv_t (average_delay);
FOR ALL : n2 USE ENTITY WORK.nand2_t (average_delay);
FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay);
-- Intermediate signals
SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, im9, im10 : BIT;
BEGIN
-- a_gt_b output
g0 : n1 GENERIC MAP (2 NS, 4 NS) PORT MAP (a, im1);
g1 : n1 GENERIC MAP (2 NS, 4 NS) PORT MAP (b, im2);
g2 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (a, im2, im3);
g3 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (a, gt, im4);
g4 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im2, gt, im5);
g5 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im3, im4, im5, a_gt_b);
-- a_eq_b output
g6 : n3 GENERIC MAP (4 NS, 6 NS) PORT MAP (im1, im2, eq, im6);
. . .
-- a_lt_b output
g9 : n2 GENERIC MAP (3 NS, 5 NS) PORT MAP (im1, b, im8);
. . .
END fixed_delay;

• Component declarations contain generics
  
• Component instantiation contain generic values
  
• Generic values overwrite default values
  

Design_Organization.parametrization.passing_values

• To pass values, upper level units must contain generics
  
• A timed bit_comparator is developed

Design_Organization.parametrization.passing_values

• Component declarations include generics
  
• Component instantiations include passed values
  
• Generic maps are required
  

Design_Organization.parametrization.passing_values

• Composition aspect corresponds to VHDL code
  
• Generics are shown by dotted lines
  
• All Architectures are average_delay
  

Design_Organization.parametrization.passing_values

• Using bit_comparator_t in a larger design
  
• Specification of generic parameters is required
  
• Exclusion of Generic Map leaves all parameters OPEN
  
• Association with OPEN causes default values to be used

Design_Organization.Passing_values.OPEN

ARCHITECTURE iterative OF nibble_comparator IS
. . .
BEGIN
c0: comp1
GENERIC MAP (tplh3 => 8 NS, tphl3 => 10 NS)
PORT MAP (a(0), b(0), gt, eq, lt, im(0), im(1), im(2));
. . .
END iterative;

• A Generic Map can specify only some of the parameters
  
• Using OPEN causes use of default values
  
• Alternatively, association by name can be used
  
• Same applies to Port Map

Design_Organization.design_configuration

• Will present examples for configuration of unbound designs
  
• A general purpose testbench
  
• The comp4 component is unbound
  
• Configure it to test any of the previous nibble_comparators

Design_Organization.configuration.testbench

CONFIGURATION average_delay OF nibble_comparator_test_bench IS
FOR customizable
FOR a1 : comp4
USE ENTITY WORK.nibble_comparator (iterative);
END FOR;
END FOR;
END average_delay;

• Configuration of testbench requires binding of a1:comp4
  
• Bind a1:comp4 to a nibble_comparator architechture
  
• Testbench configured for
  

1) Structural architecture of nibble_comparator

2) Iterative architecture of nibble_comparator

---

Design_Organization.configuration.syntax

• Syntax details of configuration declaration
  
• Block configuration gives visibility
  
• Component configuration configures a component

Design_Organization.configuration.nesting

• Will demonstrate nesting by two levels of flexibility
  
• Flexible nibble_comparator
  
• No particular bit_comparator is specified
  
• Using customizable testbench creates flexibility for:
  

1) Specifying nibble_comparator for testbench

2) Specifying bit_comparator for nibble_comparator

---

Design_Organization.configuration.nesting

• Nested configuration binds nibble and bit comparators
  

Design_Organization.configuration.nesting

• Configuring customizable testbench for testing
  

default_delay bit_comparator

instantiated through

flexible nibble_comparator

• Visibility is obtained before component configuration is done

USE WORK.ALL;
CONFIGURATION fixed_bit_level OF nibble_comparator_test_bench IS
FOR customizable
FOR a1 : comp4
USE ENTITY WORK.nibble_comparator(flexible);
FOR flexible
FOR c0, c3: comp1
USE ENTITY WORK.bit_comparator (fixed_delay);
END FOR;
FOR c1to2
FOR c: comp1
USE ENTITY WORK.bit_comparator (fixed_delay);
END FOR;
END FOR;
END FOR;
END FOR;
END FOR;
END fixed_bit_level;

• Configuring customizable testbench for testing
  

fixed_delay bit_comparator

instantiated through

flexible nibble_comparator

• Visibility is obtained before component configuration is done

Design_Organization.configuration.generics

• Configuring testbench for passed_delay bit_comparator_t
  

Design_Organization.design_configure.generics

• bit_comparator_t uses generic parameters
  
• Configure for:
  

Component binding, and Generic Map specification

• Association by name is used
  
• Same can be done with Port Map
  
• FOR c1to2 gives visibility to inside of generate

Design_Organization.configuration.syntax

• Syntax details of block configuration

Design_Organization.configuration.n_bit_register

FORMING AN n-BIT REGISTER FROM BASIC GATES

• NAND gates form sr_latch
  
• Add an inverter to form d_latch
  
• n d_latch structures form an n-bit register
  

Design_Organization.configuration.n_bit_register

ENTITY d_latch IS PORT (d, c : IN BIT; q : OUT BIT); END d_latch;
ARCHITECTURE sr_based OF d_latch IS
COMPONENT sr PORT (s, r, c : IN BIT; q : OUT BIT); END COMPONENT;
COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT;
SIGNAL dbar : BIT;
BEGIN
c1 : sr PORT MAP (d, dbar, c, q); c2 : n1 PORT MAP (d, dbar);
END sr_based;

ENTITY d_register IS
PORT (d : IN BIT_VECTOR (7 DOWNTO 0); c : IN BIT;
q : OUT BIT_VECTOR (7 DOWNTO 0) );
END d_register;
ARCHITECTURE latch_based OF d_register IS
COMPONENT dl PORT (d, c : IN BIT; q : OUT BIT); END COMPONENT;
BEGIN
dn : FOR i IN d'RANGE GENERATE
di : dl PORT MAP (d(i), c, q(i));
END GENERATE;
END latch_based;

• gate_level sr_latch uses unbound gate components
  
• sr_based d_latch uses unbound sr_latch and gate
  
• latch_based d_register uses unbound d_latch components

Design_Organization.configuration.n_bit_register

• Composition aspect shows wiring and configuration
  
• Only one of the n bits is shown
  
• Must pass through Generate statement to see d_latch
  
• Different delay values remedy the oscillation problem
  

Design_Organization.configuration.n_bit_register

• Configuring latch_based of d_register
  
• Configuration name is average_gate_delay
  
• To avoid timing problem: g2,g4 delays are at 5NS, 6NS
  

g1,g3 delays are at 2NS, 4NS

---

Design_Organization.configuration.n_bit_register

• Configuration constructs of average_gate_delay
  

Design_Organization.configuration.n_bit_register

• For g2 and g4 use NAND3 in place of NAND2
  
• This also eliminates the timing problem
  
• Port Map overwrites default in component declaration
  

Design_Organization.configuration.n_bit_register

• Instantiating n-bit register in a testbench
  
• Associating d with an 8 bit vector makes an 8-bit register
  
• X is used for Hex, O for Octal, B for Binary
  
• Can use _ (underscore) for separation, better readability
  

Design_Organization.configuration.parity_checker

ENTITY inv_t IS
GENERIC (tplh : TIME := 5 NS; tphl : TIME := 3 NS);
PORT (i1 : IN BIT; o1 : OUT BIT);
END inv_t;
--
ARCHITECTURE average_delay OF inv_t IS
BEGIN
o1 <= NOT i1 AFTER (tplh + tphl) / 2;
END average_delay;

• Develop an eight bit parity checker
  
• Use an XOR gate and an inverter

Design_Organization.configuration.parity_checker

• Use chain of XOR gates
  
• Generate statement builds the middle 6 gates

Design_Organization.configuration.parity_checker

• Iterative architecture needs to be configured
  
• Specify binding for all x2 and n1
  

Design_Organization.configuration.parity_checker

• Configuration specifies binding and generics
  
• Due to fanout, we assume last gate has a higher delay
  
• Element 6 of generate statement specifies 6 NS, 7 NS delays
  
• Other generated elements use 5 NS, 5 NS
  
• Can use OTHERS for indexing all other instantiations
  

Design_Organization.libraries

LIBRARY "ls7400" User: ... Date: ...

simple_gates PACKAGE DECLARATION ...

inv ENTITY ...

inv (single_delay) ARCHITECTURE ...

nand2 ENTITY ...

nand2 (single_delay) ARCHITECTURE ...

nand3 ENTITY ...

nand3 (single_delay) ARCHITECTURE ...

• A library can hold
  
• PACKAGE DECLARATIONS
  
• PACKAGE BODY
  
• ENTITY
  
• ARCHITECTURE
  
• Library managment is platform dependent
  

Design_Organization.libraries

• WORK is the default working library
  
• WORK is always visible

• VHDL includes STD library
  
• STD contains STANDARD and TEXTIO package
  
• STD library is always visible

• Other user libraries can be created

• Library utilization:
  
• To specify use of a library:
  

LIBRARY my_lib

• To specify use of all library contents:
  

USE my_lib.ALL

• To specify use of a package:
  

USE my_lib.my_pack

• To specify use of all contents of a package:
  

USE my_lib.my_pack.ALL

---

Design_Organization.libraries

• Assume library ls7400 contains simple_gates package
  
• Assume simple_gates package contains component declarations
  
• All component declarations are visible

Design_Organization.libraries

• Entities and Architectures in ls7400 have become visible
  
• nand2 (single_delay) from ls7400 is used
  
• In the rest of this tutorial, basic_utilities package will be used
  
• basic_utilities contains handy declarations and subprograms

Design_Organization.conclusions

2. Review: Behavioral description, Using process statements, Top-down design, Using available components, Wiring predefined components, Wiring from bottom to top, Generation of testbench data, Using procedures

3. VHDL_Timing: Modeling requirements, Objects & classes, Signals & variables, Concurrent & sequential assignments, Events, transactions & delta delays, Delay modeling, Sequential placement of transactions, Conventions

4. Structural_Description_of_Hardware: Wiring parts into larger designs, Start with primitives, Wire gates into general purpose components, Use iterative constructs, Generate testbenches, Show binding alternatives, Use gate-based components for a larger design

5. Design_Organization: Subprograms, Packaging, Parameter specification, Parametrization, Top level configuration, Design libraries, A complete example

6. Utilities_for_high_level_descriptions: Language aspects, Types, Over loading subprograms operators, Predefined Attributes, User defined attributes

7. Dataflow: Constructs for dataflow descriptions, Multiplexing and clocking, Multiple assignments, State machines, Open collector gates, A complete dataflow example, Load dependent timing

8. Behavioral_Descriptions: Constructs for sequential descriptions, Assertion for behavioral checks, Handshaking constructs, Timing control, Formatted I/O, MSI parts, A complete MSI based design

9. STANDARDS: MVL9: logic value system, Logic type, Operators, Conversions; VHDL'93: Operators, Delay model, Instantiation, Binding, Attributes, Signal assignments, Report, Postponed process