• Digital system design process
  
• Hardware description languages
  
• Hardware Design Tools:
  
• Hardware simulation
  
• Hardware synthesis
  
  
  
  
  

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• VHDL is a tool for advancing design process
  
  
  
  
  

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• Steps required for transforming design idea into hardware
  
• Each step has its representation format
  
  
  
  
  

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• A possible representation of data path information
  
• Next step is to transform into gates
  
  
  
  
  

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Design entry

Simulation

Synthesis

Test generation

• Design automation helps transforming one format to another
  
• HDLs provide uniforms data formats
  
  
  
  
  

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Behavioral
Describes System Behavioral

Dataflow
Describes System at Register and Bus Level

Structural
Describes System at Component Level

• HDLs at various levels help different design steps
  
• Behavioral, Dataflow and Structural
  
  
  
  
  

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mark1 :=
BEGIN

• memory.state **
  

• processor.state **
  

• instruction.execution ** {tc}
  

• ISPS an early behavioral HDL
  
• Description shows MARK1 CPU
  
• Clocking is not explicitly specified
  
• High degree of readability
  
  
  
  
  

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AHPLMODEL: multiplier.

MEMORY: ac1[4]; ac2[4]; count[2]; extra[4]; busy.

EXINPUTS: dataready.

EXBUSES: inputbus[8].

OUTPUTS: result[8]; done.

CLUNITS: INC[2](count); ADD[5](extra; ac2);

1 ac1 <= inputbus[0:3]; ac2 <= inputbus[4:7];

extra <= 4$0;

=> (~ ^dataready)/(1).

2 busy <= \1\;

=> (~ ^ac1[3])/(4).

3 extra <= ADD[1:4](extra; ac2).

4 extra, ac1 <= \0\, extra, ac1[0:2];

count <= INC(count);

=> (^(&/count))/(2).

5 result = extra, ac1; done = \1\; busy <= \0\;

=> (1).

END SEQUENCE

CONTROLLERS(1).

END.

• AHPL, A Hardware Programming Language
  
• Description shows an add_shift serial multiplier
  
• Clocking is explicitly specified
  
• Gate level timing is not known from this description
  
  
  
  
  

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• Another level of abstraction is at the structural level
  
• Interconnection of components is specified
  
  
  
  
  

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CCT full_adder (a, b, c, s, co)

XOR (RISE = 16, FALL = 12)

g1 (w1, a, b),

g2 (s, w1, c);

AND (RISE4 = 12, FALL = 10)

g2 (w2, c, b),

g3 (w3, c, a),

g4 (w4, b, a);

OR (RISE = 12, FALL = 10)

g6 (co, w2, w3, w4);

INPUT a, b, c;

WIRE w1, w2, w3, w4;

OUTPUT s, co;

END CIRCUIT full_adder

• Full adder of previous slide is described in GHDL
  
• Complete timing at gate level is known by this description
  
• Hard to extract functionality by reading the description
  
  
  
  
  

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Simulation:
Describe system and operation

Synthesis:
Describe system and automatically generate hardware

• Simulation and synthesis are two main HDL based tool
  
• Can simulate and synthesize with any level of abstraction
  
  
  
  
  

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• Simulation tools verify transformation at each step
  
• Verify each step before going to next
  
  
  
  
  

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• Oblivious and event driven simulation
  
• Can simulate gate level circuit with both methods
  
  
  
  
  

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• Need a tabular netlist for oblivious simulation
  
• Simulate a fixed time invervals
  
• Update table values at each interval
  
  
  
  
  

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