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Advanced VHDL: VHDL for Design and Modeling Applications

Advanced Design: CPU Design and Synthesis with VHDL

Preparation: Participants are to be prepared for this course by reviewing basic logic design concepts.

Program: This unit is the first unit in a series of three units. The unit is to be taught in 4 hours.

Prerequisites: A knowledge of digital systems and logic design is necessary.

Objectives: Participants in this training will learn the general concepts of VHDL. The use of VHDL in a design environment and general structure of the language will be discussed.

This material is to be used in conjunction with the book titled: "VHDL: Analysis and Modeling of Digital Systems", McGraw-Hill 1993, by Zainalabedin Navabi. ISBN: 0-07-046472-3

The right to copy and distribute this material in a training course is restricted and it is reserved for Zainalabedin Navabi.

"VHDL: Analysis and Modeling of Digital Systems"

A set of 60 transparency copies

Part 1: Outline
30 minutes

Part 2: Review
hour

Part 3: VHDL Timing
hour

Part 4: Structural
1 hour

Outline.history

Woods Hole, Massachusetts

VHDL, VHSIC Hardware Description Language

Woods Hole, Massachusetts 1980

IEEE 1076 standard 1993

2. Design_Environments: Digital system design process, Hardware description languages, Hardware simulation, Hardware synthesis

3. VHDL_Background: VHDL initiation, Existing languages, VHDL requirements, The VHDL language, VHDL based design process, Levels of abstraction

4. VHDL_Overview: Behavioral description, Using process statements, Top-down design, Using available components, Wiring predefined components, Wiring from bottom to top, Generation of testbench data, Using procedures