--	Model Name	: Reduced Activity - Parwan Data Path 

--	Author		: Zainalabedin Navabi 

--	Last Updated	: 09 / 15 / 1996

--	This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY WORK;
USE WORK.synthesis_parameters.ALL;
USE WORK.synthesis_utilities.ALL;
USE WORK.global_environment.ALL;
--
ENTITY par_data_path IS
    PORT (
      -- register controls:
      load_ac, zero_ac,
      load_ir,
      increment_pc, load_page_pc, load_offset_pc, reset_pc,
      load_page_mar, load_offset_mar,
      load_sr, cm_carry_sr,
      -- bus connections:
      pc_on_mar_page_bus, ir_on_mar_page_bus,
      pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
      pc_offset_on_dbus, obus_on_dbus, databus_on_dbus,
      mar_on_adbus,
      dbus_on_databus,
      -- logic unit function control inputs:
      arith_shift_left, arith_shift_right, no_shift,
      alu_operate : IN std_logic;
      alu_code : IN std_logic_vector (2 DOWNTO 0)
      );
END par_data_path;
--
ARCHITECTURE structural_synthesizable OF par_data_path IS
    --
    COMPONENT accumulator_unit PORT (load, zero : IN std_logic); END COMPONENT;
    --
    COMPONENT instruction_register_unit PORT (load : IN std_logic); END COMPONENT;
    --
    COMPONENT program_counter_unit
      PORT (increment, load_page, load_offset, reset : IN std_logic);
    END COMPONENT;
    --
    COMPONENT memory_address_register_unit
      PORT (load_page, load_offset : IN std_logic);
    END COMPONENT;
    --
    COMPONENT status_register_unit PORT (load, cm_carry : IN std_logic ); END COMPONENT;
    --
    COMPONENT arithmetic_logic_unit
      PORT (code : IN std_logic_vector; alu_operate : IN std_logic);
    END COMPONENT;
    --
    COMPONENT shifter_unit
      PORT (arith_shift_left, arith_shift_right, no_shift : IN std_logic);
    END COMPONENT;
BEGIN
    -- bus connections --
    --
    PROCESS (dbus_on_mar_offset_bus)
    BEGIN
      mar_bus (7 DOWNTO 0) := dbus;
    END PROCESS;
    --
    PROCESS
    BEGIN
      databus := dbus;
      WAIT ON dbus_on_databus;
    END PROCESS;
    --
    PROCESS (obus_on_dbus)
    BEGIN
      dbus := obus;
    END PROCESS;
    --
    PROCESS (databus_on_dbus)
    BEGIN
      dbus := databus;
    END PROCESS;

    -- register connections --
    --
    r1: accumulator_unit PORT MAP (load_ac, zero_ac);
    --
    r2: instruction_register_unit PORT MAP (load_ir);

    PROCESS (ir_on_mar_page_bus)
    BEGIN

      mar_bus (11 DOWNTO 8) := ir_out (3 DOWNTO 0);
    END PROCESS;
    --
    r3: program_counter_unit PORT MAP (increment_pc, load_page_pc, load_offset_pc, reset_pc);

    PROCESS
    BEGIN

      wait for 0 fs;
      mar_bus (11 DOWNTO 8) := pc_out (11 DOWNTO 8);
      WAIT ON pc_on_mar_page_bus;
    END PROCESS;

    PROCESS (pc_on_mar_offset_bus)
    BEGIN

      mar_bus (7 DOWNTO 0) := pc_out (7 DOWNTO 0);
    END PROCESS;

    PROCESS (pc_offset_on_dbus)
    BEGIN

      dbus := pc_out (7 DOWNTO 0);
    END PROCESS;
    --
    r4: memory_address_register_unit PORT MAP (load_page_mar, load_offset_mar);
    PROCESS
    BEGIN
      adbus := mar_out;
      WAIT ON mar_on_adbus;
    END PROCESS;
    --
    r5: status_register_unit PORT MAP (load_sr, cm_carry_sr);
    --
    -- connection of logical and register structures --
    --
    l1: arithmetic_logic_unit PORT MAP (alu_code, alu_operate);
    l2: shifter_unit PORT MAP (arith_shift_left, arith_shift_right, no_shift);
END structural_synthesizable;