-- Model Name : Procedural - Parwan Memory -- Author : Zainalabedin Navabi -- Last Updated : 09 / 15 / 1996 -- This document is © copyrighted by the Author.



LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
USE EXEMPLAR.exemplar.ALL;
--
LIBRARY WORK;
USE WORK.ParFunctional.ALL;
USE WORK.synthesis_parameters.ALL;
USE WORK.synthesis_utilities.ALL;
--
ENTITY parwan_memory IS
  PORT (read, write : IN std_logic);
END parwan_memory;
--
ARCHITECTURE behavioral OF parwan_memory IS
  TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF std_logic_vector ( 7 DOWNTO 0 );
--  SIGNAL da : std_logic_vector ( 7 DOWNTO 0 );
--  SIGNAL ad : std_logic_vector ( 11 DOWNTO 0 );
BEGIN
  mem : PROCESS 
  VARIABLE memory : byte_memory ( 0 TO 63 ) := 
    ("11100001", "11101000", "00010000", "00100111",  --cla --asl --lda,i p1 --39
     "01010000", "00101000", "10110000", "00101001",  --add,i p2 --40 --sta,i p3 --41
     "11100001", "11101000", "00000000", "00100111",  --cla --asl --lda p1 --39
     "01000000", "00101010", "11100001", "11101000",  --add #0 --42 --cla --asl
     "00000000", "00101000", "01000000", "00101010",  --lda p2 --40 --add #0 --42
     "11100001", "11101000", "00000000", "00101001",  --cla --asl --lda p3 --41
     "01000000", "00101010", "11100001", "11101000",  --add #0 --42 --cla --asl
     "00000000", "00101011", "01100000", "00101100",  --lda count --43 --sub #1 --44
     "11110010", "00100110", "10100000", "00101011",  --bra_z  end --38 --sta count --43
     "10000000", "00000000", "11101111", "00101101",  --jmp --00 --halt --p1 
     "00101110", "00101111", "00000000", "11111111",  --p2 --p3 --#0 --count=128
     "00000001", "00000001", "00000010", "00000000",  --#1 --data --data --data
     "00000000", "00000000", "00000000", "00000000",
     "00000000", "00000000", "00000000", "00000000",
     "00000000", "00000000", "00000000", "00000000",
     "00000000", "00000000", "00000000", "00000000" );
    VARIABLE ia : INTEGER;
  BEGIN
    IF read = '1' OR write = '1' THEN
      WAIT FOR 1 FS;
      ia := evec2int (adbus);
      IF read = '1' THEN 
        IF ia >= 64 THEN 
          databus := "ZZZZZZZZ";
        ELSE
          databus := memory (ia);
        END IF;
      ELSIF write = '1' THEN
        IF ia < 64 THEN
          memory (ia) := databus;
        END IF;
      END IF;
--      da <= databus; ad <= adbus;
      WAIT ON cck;
      databus := "ZZZZZZZZ";
    END IF;
    WAIT ON read, write;
  END PROCESS mem;
END behavioral;