LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
USE EXEMPLAR.exemplar.ALL;
--
LIBRARY WORK;
USE WORK.ParFunctional.ALL;
USE WORK.synthesis_parameters.ALL;
USE WORK.synthesis_utilities.ALL;
--
ENTITY parwan_tester IS
END parwan_tester;
--
ARCHITECTURE input_output OF parwan_tester IS
  COMPONENT parwan 
    PORT (interrupt : IN std_logic;  read_mem, write_mem : OUT std_logic);
  END COMPONENT;
  FOR cpu : parwan USE ENTITY WORK.par_central_processing_unit(functional);
  COMPONENT parmem PORT (read, write : IN std_logic); END COMPONENT;
  FOR mem : parmem USE ENTITY WORK.parwan_memory (behavioral);
  SIGNAL clock, interrupt, read, write : std_logic := '0';
  SIGNAL data : byte;
  SIGNAL address : twelve;
BEGIN
  clk : clock <= NOT clock AFTER 2 US WHEN halt='0' ELSE clock;
  int : interrupt <= '1', '0' AFTER 4500 NS;
  ck2 : cck <= clock;
--  PROCESS (clock) BEGIN data <= databus; address <= adbus; END PROCESS;
  cpu : parwan PORT MAP (interrupt, read, write);
  mem : parmem PORT MAP (read, write);
 -- dump_signal <= '1' WHEN halt='1';
END input_output;