--	Model Name	: Synthesizable Dataflow -  Status Register 

--	Author		: Zainalabedin Navabi 

--	Last Updated	: 09 / 15 / 1996

--	This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY parwan_s;
USE parwan_s.synthesis_parameters.ALL;
USE parwan_s.synthesis_utilities.ALL;
--
ENTITY status_register_unit IS
    PORT (in_flags : IN nibble; out_status : OUT nibble;
      load, cm_carry, ck : IN std_logic );
END status_register_unit;
--
ARCHITECTURE synthesizable_behavioral OF status_register_unit IS
    SIGNAL status : nibble := "0000";
BEGIN
    clocking: PROCESS (ck)
    BEGIN
      IF ( ck'EVENT AND ck = '0') THEN
        IF (load = '1') THEN
          status <= in_flags;
        ELSIF (cm_carry = '1') THEN
          status (2) <= NOT status (2); --c flag
        END IF;
      END IF;
    END PROCESS;
    assigning: PROCESS (status)
    BEGIN
      out_status <= status;
    END PROCESS;
END synthesizable_behavioral;