-- Model Name : Synthesizable Dataflow - Shifter
-- Author : Zainalabedin Navabi
-- Last Updated : 09 / 15 / 1996
-- This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY parwan_s;
USE parwan_s.synthesis_parameters.ALL;
USE parwan_s.synthesis_utilities.ALL;
--
ENTITY shifter_unit IS
PORT (alu_side : IN byte; arith_shift_left, arith_shift_right : IN std_logic;
in_flags : IN nibble; obus_side : OUT byte; out_flags : OUT nibble);
END shifter_unit;
--
ARCHITECTURE synthesizable_behavioral OF shifter_unit IS
BEGIN
coding: PROCESS (alu_side, arith_shift_left, arith_shift_right, in_flags)
VARIABLE t : std_logic_vector (7 DOWNTO 0);
VARIABLE v, c, z, n : std_logic; --in_flags 3210
BEGIN
IF arith_shift_left = '1' THEN
t := alu_side (6 DOWNTO 0) & '0';
n := t (7);
z := NOT all_or (t);
c := alu_side (7);
v := alu_side (6) XOR alu_side (7);
ELSIF arith_shift_right = '1' THEN
t := alu_side (7) & alu_side (7 DOWNTO 1);
n := t (7);
z := NOT all_or (t);
c := in_flags(2);
v := in_flags(3);
ELSE -- none are '1'
t := alu_side (7 DOWNTO 0);
n := in_flags(0);
z := in_flags(1);
c := in_flags(2);
v := in_flags(3);
END IF;
obus_side <= t;
out_flags <= v & c & z & n;
END PROCESS coding;
END synthesizable_behavioral;