--	Model Name	: Synthesizable Dataflow -  Program Counter 

--	Author		: Zainalabedin Navabi 

--	Last Updated	: 09 / 15 / 1996

--	This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
USE EXEMPLAR.exemplar.ALL;
--
LIBRARY parwan_s;
USE parwan_s.synthesis_parameters.ALL;
USE parwan_s.synthesis_utilities.ALL;
--
ENTITY program_counter_unit IS
    PORT (i12 : IN twelve; o12 : OUT twelve;
      increment, load_page, load_offset, reset, ck : IN std_logic);
END program_counter_unit;
--
ARCHITECTURE synthesizable_behavioral OF program_counter_unit IS
    SIGNAL count : twelve := zero_12;
BEGIN
    clocking : PROCESS (ck)
    BEGIN
      IF ( ck'EVENT AND ck = '0' ) THEN
        IF reset = '1' THEN
          count <= zero_12;
        ELSIF increment = '1' THEN
          count <= count + "01";
        ELSE
          IF load_page = '1' THEN
            count (11 DOWNTO 8) <= i12 (11 DOWNTO 8);
          END IF;
          IF load_offset = '1' THEN
            count (7 DOWNTO 0) <= i12 (7 DOWNTO 0);
          END IF;
        END IF;
      END IF;
    END PROCESS;
    outputting: PROCESS (count)
    BEGIN --using o12 in clocking, would imply registered o12
      o12 <= count;
    END PROCESS;
END synthesizable_behavioral;