--	Model Name	: Synthesizable Dataflow - Parwan CPU

--	Author		: Zainalabedin Navabi 

--	Last Updated	: 09 / 15 / 1996

--	This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY parwan_s;
USE parwan_s.synthesis_parameters.ALL;
USE parwan_s.synthesis_utilities.ALL;
--
ENTITY par_central_processing_unit IS
    PORT (clk : IN std_logic;
      interrupt : IN std_logic;
      read_mem, write_mem : OUT std_logic;
      databus : INOUT byte := "ZZZZZZZZ"; adbus : OUT twelve;
      halted : OUT std_logic := '0'; ready : IN std_logic
      );
END par_central_processing_unit;
--
ARCHITECTURE dataflow_synthesizable OF par_central_processing_unit IS
    --
    COMPONENT par_data_path
      PORT (databus : INOUT byte; adbus : OUT twelve;
        clk : IN std_logic;
        load_ac, zero_ac,
        load_ir,
        increment_pc, load_page_pc, load_offset_pc, reset_pc,
        load_page_mar, load_offset_mar,
        load_sr, cm_carry_sr,
        pc_on_mar_page_bus, ir_on_mar_page_bus,
        pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
        pc_offset_on_dbus, obus_on_dbus, databus_on_dbus,
        mar_on_adbus,
        dbus_on_databus,
        arith_shift_left, arith_shift_right : IN std_logic;
        alu_code : IN std_logic_vector (2 DOWNTO 0);
        ir_lines : OUT byte; status : OUT nibble
        );
    END COMPONENT;
    FOR data: par_data_path USE ENTITY WORK.par_data_path (structural_synthesizable);
    --
    COMPONENT par_control_unit
      PORT (clk : IN std_logic;
        load_ac, zero_ac,
        load_ir,
        increment_pc, load_page_pc, load_offset_pc, reset_pc,
        load_page_mar, load_offset_mar,
        load_sr, cm_carry_sr,
        pc_on_mar_page_bus, ir_on_mar_page_bus,
        pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
        pc_offset_on_dbus, obus_on_dbus, databus_on_dbus,
        mar_on_adbus,
        dbus_on_databus,
        arith_shift_left, arith_shift_right : OUT std_logic;
        alu_code : OUT std_logic_vector (2 DOWNTO 0);
        ir_lines : IN byte; status : IN nibble;
        read_mem, write_mem : OUT std_logic; interrupt : IN std_logic;
        halted : OUT std_logic; ready : IN std_logic
        );
    END COMPONENT;
    FOR ctrl: par_control_unit USE ENTITY WORK.par_control_unit (dataflow_synthesizable);
    --
    SIGNAL load_ac, zero_ac,
      load_ir,
      increment_pc, load_page_pc, load_offset_pc, reset_pc,
      load_page_mar, load_offset_mar,
      load_sr, cm_carry_sr,
      pc_on_mar_page_bus, ir_on_mar_page_bus,
      pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
      pc_offset_on_dbus, obus_on_dbus, databus_on_dbus,
      mar_on_adbus,
      dbus_on_databus,
      arith_shift_left, arith_shift_right : std_logic;
    SIGNAL alu_code : std_logic_vector (2 DOWNTO 0);
    SIGNAL ir_lines : byte;
    SIGNAL status : nibble;
BEGIN
    data: par_data_path PORT MAP
      (databus, adbus,
      clk,
      load_ac, zero_ac,
      load_ir,
      increment_pc, load_page_pc, load_offset_pc, reset_pc,
      load_page_mar, load_offset_mar,
      load_sr, cm_carry_sr,
      pc_on_mar_page_bus, ir_on_mar_page_bus,
      pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
      pc_offset_on_dbus, obus_on_dbus, databus_on_dbus,
      mar_on_adbus,
      dbus_on_databus,
      arith_shift_left, arith_shift_right,
      alu_code,
      ir_lines, status
      );
    ctrl: par_control_unit PORT MAP
      (clk,
      load_ac, zero_ac,
      load_ir,
      increment_pc, load_page_pc, load_offset_pc, reset_pc,
      load_page_mar, load_offset_mar,
      load_sr, cm_carry_sr,
      pc_on_mar_page_bus, ir_on_mar_page_bus,
      pc_on_mar_offset_bus, dbus_on_mar_offset_bus,
      pc_offset_on_dbus, obus_on_dbus, databus_on_dbus,
      mar_on_adbus,
      dbus_on_databus,
      arith_shift_left, arith_shift_right,
      alu_code,
      ir_lines, status,
      read_mem, write_mem, interrupt,
      halted, ready
      );
END dataflow_synthesizable;