-- Model Name : Synthesizable Dataflow - Memory Address Register
-- Author : Zainalabedin Navabi
-- Last Updated : 09 / 15 / 1996
-- This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY parwan_s;
USE parwan_s.synthesis_parameters.ALL;
USE parwan_s.synthesis_utilities.ALL;
--
ENTITY memory_address_register_unit IS
PORT (i12 : IN twelve; o12 : OUT twelve;
load_page, load_offset, ck : IN std_logic);
END memory_address_register_unit;
--
ARCHITECTURE synthesizable_behavioral OF memory_address_register_unit IS
BEGIN
PROCESS (ck)
BEGIN
IF ( ck'EVENT AND ck = '0' ) THEN
IF load_page = '1' THEN
o12 (11 DOWNTO 8) <= i12 (11 DOWNTO 8);
END IF;
IF load_offset = '1' THEN
o12 (7 DOWNTO 0) <= i12 (7 DOWNTO 0);
END IF;
END IF;
END PROCESS;
END synthesizable_behavioral;