--	Model Name	: Synthesizable Dataflow -  Instruction Register 

--	Author		: Zainalabedin Navabi 

--	Last Updated	: 09 / 15 / 1996

--	This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY parwan_s;
USE parwan_s.synthesis_parameters.ALL;
USE parwan_s.synthesis_utilities.ALL;
--
ENTITY instruction_register_unit IS
    PORT (i8 : IN byte; o8 : OUT byte; load, ck : IN std_logic);
END instruction_register_unit;
--
ARCHITECTURE synthesizable_behavioral OF instruction_register_unit IS
BEGIN
    PROCESS (ck)
    BEGIN
      IF (ck'EVENT AND ck = '0') THEN
        IF load = '1' THEN
          o8 <= i8;
        END IF;
      END IF;
    END PROCESS;
END synthesizable_behavioral;