LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; -- LIBRARY EXEMPLAR; USE EXEMPLAR.exemplar_1164.ALL; USE EXEMPLAR.exemplar.ALL; -- LIBRARY parwan_s; USE parwan_s.ALL; USE parwan_s.synthesis_parameters.ALL; USE parwan_s.synthesis_utilities.ALL; -- ENTITY parwan_memory IS PORT (cs : IN std_logic; rwbar : IN std_logic; databus : INOUT byte := "ZZZZZZZZ"; adbus : IN twelve ); END parwan_memory; -- ARCHITECTURE behavioral OF parwan_memory IS TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF std_logic_vector ( 7 DOWNTO 0 ); BEGIN mem : PROCESS VARIABLE memory : byte_memory ( 0 TO 63 ) := ("00000000", "00011000", "10100000", "00011001", --00: lda 24, sta 25 "00100000", "00011010", "01000000", "00011011", --04: and 26, add 27 "11100010", "11101001", "01100000", "00011100", --08: cac, asr, sub 28 "00010000", "00011101", "11000000", "00100100", --12: lda i 29, jsr 36 "11101000", "11100000", "10000000", "00100000", --16: asl, nop, jmp 32 "00000000", "00000000", "00000000", "00000000", --20: "01011100", "00000000", "01110000", "00010010", --24: (24, 25, 26, 27) "00001100", "00011111", "00000000", "01011010", --28: (28, 29, 30, 31) "10000000", "00010010", "00000000", "00000000", --32: jmp 18 "00000000", "11100010", "10010000", "00100100", --36: , cma, jmp i 36 "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000", "00000000" ); VARIABLE ia : INTEGER; BEGIN databus <= "ZZZZZZZZ"; IF cs = '1' THEN WAIT FOR 70 NS; ia := evec2int (adbus); IF rwbar = '1' THEN IF ia >= 64 THEN databus <= "ZZZZZZZZ"; ELSE databus <= memory (ia); END IF; ELSIF rwbar = '0' THEN IF ia < 64 THEN memory (ia) := databus; END IF; END IF; END IF; WAIT ON cs, adbus; WAIT FOR 50 NS; END PROCESS mem; END behavioral;