--	Model Name	: Synthesizable Behevioral - Tester 

--	Author		: Zainalabedin Navabi 

--	Last Updated	: 09 / 15 / 1996

--	This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
USE EXEMPLAR.exemplar.ALL;
--
ENTITY parwan_tester IS
END parwan_tester;
--
ARCHITECTURE input_output OF parwan_tester IS
    COMPONENT parwan PORT (clk : IN std_logic; interrupt : IN std_logic;
      read_mem, write_mem : OUT std_logic;
      databus : INOUT std_logic_vector (7 DOWNTO 0);
      adbus : OUT std_logic_vector (11 DOWNTO 0)
      );
    END COMPONENT;
    FOR cpu : parwan USE ENTITY WORK.par_central_processing_unit(behavioral_synthesizable);
    SIGNAL clock, interrupt, read, write : std_logic := '0';
    SIGNAL data : std_logic_vector ( 7 DOWNTO 0 ) := "ZZZZZZZZ";
    SIGNAL adr : INTEGER := 0;
    SIGNAL address : std_logic_vector ( 11 DOWNTO 0 );
    TYPE byte_memory IS ARRAY ( INTEGER RANGE <> ) OF std_logic_vector ( 7 DOWNTO 0 );
    BEGIN
      int : interrupt <= '1', '0' AFTER 4500 NS;
      clk : clock <= NOT clock AFTER 1 US WHEN NOW <= 100 MS ELSE clock;
      cpu : parwan PORT MAP (clock, interrupt, read, write, data, address);
      mem : PROCESS
      VARIABLE memory : byte_memory ( 0 TO 63 ) :=
        ("00000000", "00011000", "10100000", "00011001", --lda 24, sta 25
        "00100000", "00011010", "01000000", "00011011", --and 26, add 27
        "11100010", "11101001", "01100000", "00011100", --cac, asr, sub 28
        "00010000", "00011101", "11000000", "00100100", --lda i 29, jsr 36
        "11101000", "11100000", "10000000", "00100000", --asl, nop, jmp 32
        "00000000", "00000000", "00000000", "00000000",
        "01011100", "00000000", "01110000", "00010010", --(24, 25, 26, 27)
        "00001100", "00011111", "00000000", "01011010", --(28, 29, 30, 31)
        "10000000", "00010010", "00000000", "00000000", --jmp 18
        "00000000", "11100010", "10010000", "00100100", -- , cma, jmp i 36
        "00000000", "00000000", "00000000", "00000000",
        "00000000", "00000000", "00000000", "00000000",
        "00000000", "00000000", "00000000", "00000000",
        "00000000", "00000000", "00000000", "00000000",
        "00000000", "00000000", "00000000", "00000000",
        "00000000", "00000000", "00000000", "00000000" );
      VARIABLE ia : INTEGER;
    BEGIN
      WAIT UNTIL clock = '0';
      data <= "ZZZZZZZZ";
      WAIT FOR 20 NS;
      IF read = '1' OR write = '1' THEN
        ia := evec2int (address);
        adr <= ia;
        IF read = '1' THEN
          IF ia >= 64 THEN
            data <= "ZZZZZZZZ";
          ELSE
            data <= memory (ia);
          END IF;
        ELSIF write = '1' THEN
          IF ia < 64 THEN
            memory (ia) := data;
          END IF;
        END IF;
      END IF;
    END PROCESS mem;
END input_output;