Because of its large size, memory modeling requires special attention in modeling hardware systems. Variables can be used for memory modeling but they usually require large allocation of the LRU physical memory. Modeling large memories above 16 or 64 Meg may not be possible using large arrays of variables. Requiring large physical memory, coupled with interfacing with the memory for the purpose of reading and writing before and after simulation makes memory modeling an important issue in writing VHDL descriptions of large hardware systems. Our approach to this problem is the use of a paging method, so that only a portion of the memory would be resident in the physical memory at a given time. Pages that are referenced for reading or writing have a corresponding disk file. This facilitates an ASCII interface with the memory.
Main characteristics of the memory model will be discussed in this section. In the following section, more details of the model will be presented. Figure 1 shows a general structure of the memory model.
The memory model we have developed is configurable for size and page setup by the use of generic parameters. This way, any size memory can be instantiated from VHDL descriptions, without concern for the filing structure and file size. The memory has a physical part and a logic part, both these parts are partitioned into pages. Only a few pages are in the physical memory at any one time. The remaining data of the memory in the logical memory are on physical disk files. The replacement method for replacing pages from the physical memory is, and a dirty bit is used to guard against unnecessary disk writing. Disk data are compressed, and are uncompressed upon read. This saves the disk space for large memory models. Since the data in the memory is binary, compressing becomes essential for large word lengths.
Figure 1. Memory model outline
Another feature of memory model is that it only requires disk files corresponding to pages with initial data to physically exist at the start of a simulation run. If new pages are written into, new pages will be created. This feature is only supported in VHDL'93 version of the memory model. VHDL'87 file IO does not allow the implementation of this feature.
Both VHDL'93 and VHDL'87 implementations of the memory have been done. However, the 93 implementation is far more efficient and its use over the 87 version is recommended when a choice exists
The model presented in this report can be configured by the size of the memory, the memory word size, the size of the pages and the number of pages resident in the memory (page frames). The model uses generic parameters for configuring itself. There are five generic parameters passed to the model, number of address bits that indicates the memory size, number of data bits that indicates the word size of the memory, number of pages kept simultaneously in the memory, number of bits that are not masked off which indicate the page size, and a four character string that will be used in the filenames. The memory model has four input ports, address, r/wbar, cs, dump. It also has an INOUT port for the data. Each page is saved in a unique file on the disk. When a page is addressed, if there is a corresponding disk file for the page, will be read from the disk, otherwise, it will be written to the disk after it is swapped out this of the memory. This way, ASCII files will be used to represent data into the memory before simulation, and data out of the memory after simulation has been performed. By activating the dump signal the pages in the memory will be saved on the disk, even if they are not to be swapped out. This can be useful at the end of simulation to write results in files.
COMPONENT rm GENERIC
no_of_data_bits : POSITIVE := 32; no_of_pages : POSITIVE := 3 ; max_bits : POSITIVE := 15; file_name : STRING (1 TO 4) := "PAGE" );
r_wbar : IN std_logic := '1'; cs : IN std_logic := '0'; data : INOUT std_logic_vector(no_of_data_bits-1 DOWNTO 0); dump : IN BOOLEAN := FALSE ); |
. . . r : rm PORT MAP(ad, rw, cs, dt,dumping); . . . |
Figure 2. Using the memory component
Each page frame has a wazzu valid bit indicating that the page has been loaded to that frame. Initially, all valid bits are reset. For eliminating redundant write backs to the disk, there is a dirty bit for each frame. If there has been a write to that page from the time that it has been loaded to the memory the dirty bit will be set. The LRU page replacement technique is used and there is an LRU counter for each page frame. When a page is accessed its LRU counter will be set to zero, and with each memory access all the counters are incremented by one. The page picked for replacement is the one with maximum counter value. If the dirty bit for this page is set then it will be written back to the disk before the new page is swapped in.
When a word is accessed for either read or write, its address indicates its page number. A search is done in the page table to see if that page is in the memory. If it does not appear in the page table, using the LRU replacement technique a page will be selected to be swapped to the disk. The page to which read or write is to be done will replace the least recently used page. At this point the page frame that contains the addressed page is known. Depending on the value of the r/wbar signal, read or write will take place. If a write takes place, the dirty bit of that page will be set.
Using the memory model is done in VHDL by instantiation of the ram component as shown below. Memory size, page size, number of page frames, and word size are specified by use of generic parameters. Component declaration of the memory and its instantiation are shown in Figure 2.
The original code of the memory model has been modified to compile and simulate on a VHDL'87 simulation environment. This version has major disadvantages over the VHDL'93 version. The most critical problem is that in the 87 version all the disk files corresponding to the logical memory must exist before starting the simulation. This is due to the fact that VHDL'87 does not support file open and cannot check to see if a file exits .