9.1. Write a VHDL description for a D-type flip-flop with a d input, asynchronous set and reset inputs, with q and qb outputs. Use three delay parameters for set-input to q, reset-input to q, and d-input to q (as in Figure 9.7). Your description should have only one delta delay between the input and output changes and for the nonzero delay values the delta delay should not appear on the output.

9.2. Write an assertion statement to issue a warning message if a negative pulse shorter than 1 us appears on the input clock.

9.3. Write an assertion statement to issue a warning message if the frequency of the observing clock is lower that 100 KHz. If the clock is too slow in some MOS circuit, the circuit loses information. Assume symmetrical clock pulses.

9.4. Modify this description of in Figure 9.22 to one for a Mealy machine detecting the same sequence. Write a test bench and compare the Mealy and Moore machine outputs.

9.5. Write a behavioral description for a Mealy machine that continuously monitors its x input for the 11010 sequence. When the sequence is found, the output becomes ‘1’, and it returns to ‘0’ with the clock. The circuit has a synchronous reset input that resets the circuit to its initial state when it becomes ‘1’.

9.6. Write a description for an asynchronous circuit that generates one positive pulse for every two complete positive pulses that appear on its input. Use wait statements and processes.

9.7. Write a behavioral description for a divide-by-n circuit in which n is passed to it via a generic parameter. The circuit has an x input and a z output. For every n positive pulse on x, one positive pulse should appear on z.

9.8. Generate two phases of a clock using a single triggering signal as input as shown below. Width of the short pulses on the triggering signal determine the time that both phases are zero. Use wait and process statements.

9.9. Write a behavioral description for modeling an asynchronous circuit. The circuit has inputs x and y, and output z. If a 0-to-1 transition on x is immediately followed by a 1-to-0 transition on y (with no other transitions on either input between these two transitions), the output becomes '1'. The output stays high until either x changes to '0' or y changes to '1'. Use process and wait statements.

9.10. Write a process to output a 4-bit BIT_VECTOR signal in hexadecimal. When an event occurs on the signal, the process becomes active, and it writes the time and the hexadecimal representation of the signal to an output file. To test this process, use it in a description of a synchronous binary up-counter, and output the counter output to a file named hex.out. You may use the utilities in the basic_utilities package. The statement shows a simple implementation of the binary counter:

count <= inc (count) WHEN clk = ‘1’ AND clk’EVENT ELSE count;

9.11. Write a procedure (print_hex) to convert an unconstrained BIT_VECTOR to a string of hexadecimal digits and print it to a declared file. The subprogram declaration should be specified this way:

PROCEDURE print_hex (VARIABLE hex : OUT TEXT; bin : BIT_VECTOR);

In this declaration, hex is the open text file object to which writing is to be done, and bin is the binary data to be printed. Use this procedure in a description of a synchronous binary up-counter to verify its functioning. Use the method suggested in Problem 9.10 to implement the counter.

9.12. Write a procedure for reading hexadecimal data from a text file. When the procedure is called, it reads a new line from the file. Each line consists of time and hex data separated by a space. The hex data needs to be converted to binary data and then assigned to a target signal parameter in the procedure at the specified time. The subprogram declaration should be stated this way:

PROCEDURE assign_hex (SIGNAL bin : OUT BIT_VECTOR;

VARIABLE success : OUT BOOLEAN; VARIABLE hex_data : IN TEXT);

When the procedure is called, it reads a line of a file object passed to it via the hex_data parameter and assigns the data read from the file to the bin signal. If an end-of-file is reached and the reading is not successful, the success output of the procedure becomes FALSE. To verify the behavior of this procedure, use it in a process statement and assign the values read from a test file to a signal output in your test description.

9.13. A 4-bit shift register has a mode, a serial_input, and clock inputs as well as four parallel_input lines. The four lines of outputs are parallel_output. When mode is high, the shift register is in the right-shift mode and on the falling edge of the clock, the serial_input is clocked into the shift register. When mode is low, on the falling edge of the clock, the parallel_input is loaded into the shift register. A) For this shift register, write an entity with a generic delay. With this delay proper output appears on the parallel_output the falling edge of the clock. B) Write the pure behavioral architectural body for this shift register. Be sure to use the generic delay for the final output.

9.14. Use a process statement to develop a behavioral description for a Toggle flip-flop. The flip-flop has a single t input and two q and nq outputs. After the rising edge of the t input, the two outputs will be complemented. The q output has a low-to-high propagation delay of q_tplh and a high-to-low propagation delay of q_tphl. The nq output has a low-to-high propagation delay of nq_tplh and a high-to-low propagation delay of nq_tphl. Pass the propagation delays as generic parameters and use them in your behavioral description. Write the complete description using the entity declaration shown here:

ENTITY t_ff IS

GENERIC( q_tplh, q_tphl, nq_tplh, nq_tphl : TIME);

PORT (t : IN BIT; q, nq OUT BIT);

END t_ff;

9.15. In this problem you will configure the T flip-flop of the previous problem. Write a description of an n-bit t_register using t_ffs of Problem 9.14. For the t_register, write a configuration declaration that uses the behavioral t_ff with q_tplh, q_tphl, nq_tplh, nq_tphl delay values of 2 ns, 4 ns, 3 ns, and 5 ns, respectively. The output of a T flip-flop has a frequency half of that of its input. Two cascaded T flip-flops can be used as a divide by four circuit. Use two configured t_registers to build a parallel 8-bit divide-by-4 circuit.

9.16. In this problem you will use a 10 value logic system of integers ranging between 0 and 9. When an input reaches value 0, it is considered low and when it reaches 9, it is considered high. A) Define the ten value type using the integer base type. B) Write a description of an inverter using this value system. When the input reaches the low level (0), the output starts switching to high, and linearly change from 0 to 9 in 30 ns. When the input reaches the high level (9), the output starts switching to low and linearly change from 9 to 0 in 20 ns. You need not be concerned about the input changing too fast for the output to respond. Model linear changes on the output only, considering only extreme low and high values at the input of the inverter.

9.17. Use the 10 value logic system in the previous problem to model waveform dependencies in logic gates. Model an inverter with an input threshold value of 5, so that the inverter starts switching to its high state when the input state crosses 5 in the downward direction and starts switching to its low state when its input crosses the threshold (5) in the upward direction. Complete transitions of the output of the inverter from high state (9) to low state (0) take 20 ns (2 ns each state), while the transitions from low to high take 30 ns (3 ns each state). The output should respond to changes on the input while making a transition, i.e., if the input switches from state 5 to 6 while the output is making a low-to-high transition, the direction of the output should change. This is not an easy problem. Also, you can easily modify this problem to make the speed of the output depend on the speed of the input.

9.18. Develop a behavioral model of an 8-bit sequential multiplier. The 4-bit version of this multiplier was discussed in Chapter 1 (Section 1.2.2). Use the same interface and signaling as the multiplier in Chapter 1, i.e., use dataready, busy and done. The circuit receives two 8-bit operands when the input dataready becomes '1'. This causes the multiplication process to begin and the busy flag to become active. Using the add-shift method, the multiplier takes one or two clock pulses for each bit of the multiplicand. When the process is completed, done becomes '1' for one clock period and busy returns to zero. The circuit receives two operands from its inputbus, and produces the result on its 8-bit result output. Your behavioral description of this circuit should model it at the clock level. That is, the number of clock pulses that the behavioral model takes for multiplication of two numbers should be the same as that of an actual circuit using the add-shift method.