7.2. Write an entity declaration and an architecture for an RC circuit in the qit logic value system. The circuit has an input and an output. The output follows the input for '0', '1' or 'X' input values. If the input becomes 'Z', the output holds its old value for several milliseconds (use 8 ms).

3. Use the RC circuit in Problem 2 to describe an NMOS two-input NAND gate. The solution to this problem depends on code developed in Problem 7.2.

7.4. Show type definition for the distance physical type, ranging from microns to meters.

7.5 Write a procedure, apply_bit, such that bits of an unconstrained string input to the procedure are applied to its target signal according to the specified time interval. Make sure no unnecessary transactions occur on the target of the procedure. A sample call to this procedure is shown here:

apply_bit (target, "110001000100001111001010", 300 NS);

7.6. Using bin2int and int2bin, write a function, inc_qits, that returns the increment of its qit_vector input parameter. The output of the function should be qit_vector type, and values 'X' and 'Z' should be treated as '1'. Use unconstrained arrays so that your function works regardless of the size of the input.

7.7. Use the concatenation operator to develop a complete VHDL description for an 8-bit logic shifter. The circuit has a 2-bit control input c. The value of c=00 is for no-operation, c=01 is for right rotate, c=10 is for left rotate, and c=11 is for arithmetic right shift. The data input and output of the circuit are of the qit_vector type, and their mapping is determined by the bits of c.

7.8. Write a procedure that assigns consecutive binary numbers to its OUT BIT_VECTOR lines. The procedure should have a target output that is an unconstrained array, and a TIME period. When called with an n-bit argument, it should assign sequential binary numbers from 0 to 2n-1 to its target signal output. These numbers are distanced by the amount of the constant associated with the period parameter. For example, if called with a 2-bit vector and a period of 100 NS, then the target will receive this data:

"00", "01" AFTER 100 NS, "10" AFTER 200 NS, "11" AFTER 300 NS;

You can use all the procedures and utilities in the basic_utilities package.

7.9. Show the overloading function for the XOR operator for the qit logic value system.

7.10. Write an unconstrained odd parity checker function. The input is of qit_vector type and the output of qit type. Treat values 'Z' and 'X' as ‘1’. The function returns the XOR results of all its input bits.

7.11. Use the function in Problem 7.10 in an architecture for functional description of a parity checker circuit.

7.12. Speed is distance/time. Write the physical type for speed. Overload the division operator to evaluate speed when it is used for dividing distance by time (see Problem 7.4).

7.13. Rewrite the int2bin procedure such that it functions properly for any size output, declared with any range, and in any direction. Treat the left bit of the output as the most significant bit and the right-most bit as the least significant. Bit 3 is the MSB For a BIT_VECTOR ranging from 3 TO 10 associated with the output and the LSB is bit 10.

7.14. Rewrite the bin2int procedure such that it functions properly for any size output, declared with any range, and in any direction. Treat the left bit of the input as the most significant bit, and the right most bit as the least significant. Bit 3 is the MSB For a BIT_VECTOR ranging from 3 TO 10 associated with the input of this procedure and the LSB is bit 10.

7.15. Write an expression for detecting the falling edge on a clock that is the qit type. Falling edge occurs only when the clock makes a transition from '1' to '0'.

7.16. The 'TRANACTION attribute toggles when a transaction occurs on its parameter. Write an expression such that it causes the value of signal e to toggle when an event occurs on a. Using this expression in the following VHDL code, show and justify all transactions and events that occur on the a, t, and e signals.

7.17. Use conditional signal assignments to describe a toggle flip-flop in qit logic value system. The output toggles when a complete positive pulse ( ‘0’ to ‘1’ to ‘0’) appears on the input.

18. Repeat Problem 7.7 for unconstrained input and output vectors. The output of the shifter should become all ‘X’ if the value c is anything but "00", "01", "10", or "11". Take advantage of array attributes.
19. Use an array of BITS as shown below to model master-slave jk flip-flop. ARRAY (BIT, BIT, BIT) OF BIT Use j, k and q values for the indices of this array, and let the array represent the next state of the flip-flop. In the declarative part of the architecture of the flip-flop declare a constant (for example, jk-table) of the type of the array shown above. Initialize this constant to appropriate next values of a jk flip-flop. In the statement part of the architecture of the flip-flop look up next q values by indexing the jk table using j, k and present q values.
20. Write an architecture that uses ll_utilities of Section 7.3.4 for entering integers (5, 10, 15, 19, 20, 31, 6, 7, 8, 9, 28, 11, 7) into the list, and removing the integer that follows 15 from the list, and finally clearing the entire list.
21. Write a procedure as part of the ll_utilities of Section 7.3.4 to remove all nodes with value v from the list.
22. Write a procedure as part of the ll_utilities of Section 7.3.4 for sorting the entries of a pointer type linked list in ascending order.
23. Write a procedure as part of the ll_utilities of Section 7.3.4 for writing all the integers of pointer type linked list to a physical file. Pass the file to this procedure. Note than integer to character conversion must be done to take advantage of character files.
24. Declare a doubly linked list and repeat Problem 7.21. For this structure, two links of the pointer type must be declared in the record of each node.

7.25. Using concurrent statements, write a VHDL code that sets an error signal (error) to ERROR if the period of an incoming clock signal ever drops below 1 US. At all other times the error signal value stays at GOOD. Declare necessary types.

7.26. ou can take advantage of the basic_utilities package in this problem. Write a function (oz_count) that will return number of 1s or 0s in an unconstrained BIT_VECTOR. If the mode value of the input of the function is ONES it returns the number of 1s and if the mode input value is ZEROS it returns the number of 0s.

7.27. Write a VHDL description for a CMOS memory element with read/write control, enable and a shared input/output line. When enabled and rw=1, the output is driven by the memory. When enabled and rw=0, the input will be written into the memory. Use qit type. Using this memory element write a structural description for forming an n*m (m rows and n columns) memory array by wiring single bit elements. All input/output lines in a column are wired.