6.1. Write a function for the carry output of a full-adder.

6.2. Write a function for the sum output of a full-adder.

6.3. Write a function, inc_bits, that returns the 4-bit increment of its 4-bit input vector. Write Boolean expressions for the four bits of the output.

6.4. Using the carry and sum functions of Problems 6.1 and 6.2 write a functional description of a full-adder. Use an entity declaration with a, b and ci inputs and s and co outputs. In the functional architecture of this entity include the necessary functions. Use 21 ns and 18 ns delays for the sum and carry outputs, respectively. The solution to this problem depends on code developed in Problems 6.1 and 6.2.

6.5. The apply_data procedure in Figure 6.4 causes a transaction on its target every 500 ns even if the data on this line does not change from one time interval to another. Modify this procedure to remove unnecessary transactions.

6.6. Write a procedure, apply_bit, such that bits of a 24 bit wide string input to the procedure are applied to its target signal according to the specified time interval. Make sure no unnecessary transactions occur on the target of the procedure. A sample call to this procedure is shown here.

apply_bit (target, "110001000100001111001010", 300 NS);

6.7. Using bin2int and int2bin, write a function, inc_bin, that uses a binary input parameter and returns a binary value. The return value is the increment of the input parameter.

6.8. Write the package declaration and package body such that it includes the sum and carry of Problems 6.1 and 6.2, inc_bits of problem 6.3, apply_bit of problem 6.6, and inc_bin of problem 6.7. Use additional_utilities for the name of this package. The solution to this problem depends on code developed in Problems 6.1, 6.2, 6.3, 6.6 and 6.7.

6.9. Use the apply_bit procedure in the additional_utilities package in Problem 6.8 in a test bench for the full-adder in Problem 6.4. Use test vectors to test the full-adder for all eight input combinations. The solution to this problem depends on code developed in Problems 6.1, 6.2, 6.3, 6.6, 6.7 and 6.8.

6.10. Write an entity declaration and an average_delay architecture for an Exclusive-OR gate with a tplh of 9 ns and tphl of 7 ns. The entity declaration should contain generics for the timing parameters with the specified default values.

6.11. Use the XOR gate of Problem 6.10 and the basic gates of Figure 6.18 to write a gate level description for a full-adder. Use a configuration specification with generic map aspects to override the default values of the timing parameters of all gates with 11 ns. The solution to this problem depends on code developed in Problem 6.10.

6.12. Use the apply_bit procedure of the additional_utilities package in Problem 6.8 in a test bench for testing the full-adder in Problem 6.4 and the full-adder in Problem 6.11 in parallel. Declare two signals in this test bench to show the differences of the sum and carry outputs of the two versions of the full-adder. Use difference_sum and difference_carry for these signals, and use the XOR operation for subtracting the like signals. The solution to this problem depends on code developed in Problems 6.1, 6.2, 6.3, 6.6, 6.7, 6.8, 6.10 and 6.11.

6.13. Write a description for a full-adder using 2-input NAND and XOR gates. In this description, do not include configuration specification.

6.14. Write a configuration declaration on top of the full-adder in Problem 6.13 to bind the components of this design with the XOR gate of Problem 6.10 and the gates of Figure 6.18. Specify 11 ns in this configuration declaration for timing generic parameters of all gates. The solution to this problem depends on code developed in Problems 6.10 and 6.13.

6.15. Develop a test bench for the full-adder of Problem 6.14. The solution to this problem depends on code developed in Problems 6.10, 6.13 and 6.14.

6.16. Use generate statements to describe an 8-bit adder using the full-adders in Problem 6.13. Write a configuration declaration on top of this adder for binding the underlaying gate components of the full-adder to the XOR gate of Problem 6.10 and the gates of Figure 6.18. Using this configuration declaration, specify tplh and tphl of 10 ns and 11 ns for NAND2, and 11 ns and 13 ns for XOR. The solution to this problem depends on code developed in Problems 6.10 and 6.13.

6.17. Use the configured adder of Problem 6.16 in a test bench testing it for worst case delay. The solution to this problem depends on code developed in Problems 6.10, 6.13 and 6.16.

6.18. Write a procedure that assigns consecutive binary numbers to its OUT BIT_VECTOR lines. The parameters of the procedure are an 8-bit target output and a TIME period. When called, it will assign sequential binary numbers from 0 to 255 to its target signal output. These numbers are distanced by the amount of the constant associated with the period parameter. You can use the utilities of the basic_utilities.

6.19. Design an 8-bit odd-parity checker using the XOR gate in Problem 6.10. Use generate statements and wire the gates for minimum delay. Use the default delay values of the XOR gate. Write a test bench for testing all the input combinations of this circuit. You may use the procedure developed in Problem 6.18. The solution to this problem depends on code developed in Problems 6.10 and 6.18.

6.20. Show the gate level implementation of a Master-Slave-JK flip-flop. Use the Gates in Figure 6.18, and write a configuration declaration on top of the flip-flop. Use reasonable delay values and avoid oscillation by using different delay values for the two cross-coupled gates.