Dear ASIC/FPGA Designer

Thank you for visiting this WWW-Server.

This server is installed to collect the opinions of ASIC and FPGA designers regarding the concept of design errors and problems they can cause. Our final goal is to develope special technology extensions and synthesis algorithms that allow the designers to correct their mistakes even after the chip fabrication. (This capability is named Correctability) These mistakes are principally those design errors that are made during the design developement steps and have not been found in verification phases. In order to get more familiar to this subject, you can refer to:

"Modeling of VHDL Design Errors and Methods for their Correctability",
M.R. Movahedin, P. Kindsmüeller, W. Stechele,
VHDL International Users' Forum, Spring 1996 (VIUF'96).

or get its postscript version.

This survey will help to find out what kind of design errors have to be concentrated more on, and which imaginable ones are less important.

We appriciate your efforts in filling out this questionnaire, and will send you a copy of the processed results, if you provide us an E-mail address here:

IMPORTANT: Answer to some questions seems to be your confidential information, or violate copyright of your organization. Hereby we state, that all of the collected data will be processed absolutely confidential. It means:

  1. The log-file of this WWW-Server, which holds your host-name, will be used only for administration purposes (if any was necessary), and will be erased after a short time.
  2. Above E-mail address (if you have provided) will not be used for any intention, but sending the results to you.
  3. None of the answers will be published individually, but among others after statistical processes.
(If you need, we can also send a signed version of this statement to you).

However, you can simply leave such critical questions un-answered. The major part of them has nothing to do with any organization copyright or confidential information.

Thank you again.

Institute for Integrated Circuits
Technical University of Munich
Munich, Germany

for any question or further information, feel free to send us a message:
  M_Movahedin@lis.e-technik.tu-muenchen.de

PART 1: GENERAL QUESTIONS

  1. You are mainly involved in design of digital systems using:

    Note: if you are involved both in ASIC and FPGA designs, please fill this questionnaire two times, one time as an ASIC designer, and second as an FPGA one.

  2. The average size of your designs (excluding RAMs and ROMs) is:
  3. Which of the following design methods describes your strategy best:

    Describe the design in a high level using an HDL, and have the synthesizers make necessary resource scheduling, allocation and technology mapping automatically, and provide desired design constraints. (e.g. you are a Synopsys Behavioral Compiler user)

    Make resource scheduling and allocation manually, and let the synthesizer automatically define the data elements (registers, operators, etc.) and their bussing structure, do eventually resource sharing, map them to the technology in use, and provide desired design constraints. (e.g. you use Synopsys VHDL/HDL/Design Compiler at RTL level without involving in hardware design concepts very deeply)

    Make resource scheduling and allocation, data element selection and their bussing structure and resource sharing manually, define all of them in an HDL, use a synthesizer to translate and map it to the technology in use, and provide desired design constraints. (e.g. you are a conventional hardware designer, be always strongly aware about the structure of final design, using Synopsys VHDL/HDL/Design Compiler at RTL level)

    Do all jobs manually using schematic capture tools.

  4. As an HDL, you use:
    • VHDL
    • Verilog
  5. How many percent of your designs (chips) work quite properly in the first system it is integrated in?
  6. If your chip did not work properly in the first system integration, how many times would you have to modify your design, till that it work fairly after its integration in the whole system?
  7. Having a flawed chip in the hand, you can do some of the following tasks.
    How often can they be applied (i.e. practically possible)?

    • You do not need to be aware of design errors, because you develope your designs first in FPGAs and then translate them to ASICs. Nothing to lose, even in case of some design errors.

    • Though the chip is flawed, it is usable, however with a reduction in performance or desired features.

    • The chip is usable, however a change in the software is necessary in order to compensate the hardware flaw.

    • The chip is usable, however some extras or changes in the hardware around it are necessary in order to compensate the hardware flaw.

    • The hardware error can be corrected using Laser or Focused Ion Beam on the chip, so it would be further quite usable.

    • Unfortunately nothing, the chip is functionally not usable at all, i.e. the chip has some fatal errors.

  8. A flawed chip can not work properly in the whole system because of errors or malfunctions in its different parts, some of which are listed below.
    How often can each of them happen?

    • Malfunction or design error in the chip logic functionality.

      In this particular case, the design error lies in:

      • Data Section, i.e. data elements like registers, operators & multiplexers, and their bussing structure.

      • Control Section, i.e. the state machine that controls the operations.

    • Malfunction or error in the internal timings.

    • Malfunction or error of environmental interfaces, namely I/O specifications.

    • Error or failing in chip fabrication, that could not been detected in the fab.

  9. How often does each of the following points influence on the malfunction of a chip in a system in which the chip is integrated:

    • Mistakes and errors in the original specification, that specifies the functionality of the design and is sent to designers to develope the necessary hardware and software based on it.

    • Uncompleteness of the original specification, i.e. that some seldom happening situations are not considered carefully, and hence the designers would not be care of.

    • Errors and/or bugs in the HDL description of the design, which is developed by you or your design team and is further synthesized by a synthesizer tool.

    • Errors and/or bugs in the CAD tools. (synthesis, place&route, timing analys, functionality verification, etc.)

    • Errors in the specification and/or prediction of the environment status, with which the chip has to interface.

  10. If some methods will be developed, that would allow you to correct your design errors even after the fabrication of your ASIC (namely correctability), then you are ready to pay for its advantages with:
    • an increase in the area of the design by at most
    • a decrase in the speed of the design by at most

PART 2: (V)HDL DESIGN ERROR MODEL

The second part of this questionnaire concentrates on a (V)HDL design error model. This model is mainly based on usually used synthesizable subset of VHDL, but you can answer the questiuons, even if you are a Verilog user.

This model deals mainly with the mistakes that are made during the developement of the design HDL description, and are propagated to gate level by a synthesizer, resulting in a flawed chip. Considering this fact that a quite complete simulation and/or verification of a large design takes a long time and is practically impossible, those flaws could not be detected before chip fabrication and only after the chip takes effect in the whole system, they would be detected by observing the system malfunctions. Thus, a redesign , i.e. rewriting the HDL description and correcting its mistakes, will be necessary to achieve to a flawless chip.

The answer to this question that why these errors are happened and not detected in verification phases is behind this questionnaire, and depend strongly on the designers' design methodology. But it can not be forgotten, that no one can claim that his/her design is quite error free. The VLSI history shows that even large powerfull companies have designed and fabricated flawed microprocessors and their mistakes are detected first after a very long while.

Below, different possible and imaginable (V)HDL design errors (mostly with an example showing it more clearly) are presented. These different classes of mistakes have a very important point in common: they do not cause any syntax error and don't make the design unsynthesizable based on the synthesizable VHDL subset in used, because the HDL description after these changes should be compiled again and be synthesized as before. In each item, you are asked to define: how often they can appear, i.e. how probable they are;

  1. Mistakes in ENTITY declaration of any making up modules, including: extra or inadequate ports, false port direction, false port width.

    Example:

    Flawed VHDL Code:

    ENTITY e IS
    PORT (
    a, b, c : IN INTEGER;
    d: IN BIT_VECTOR(7 DOWNTO 0))
    END e;

    Corrected VHDL Code:

    ENTITY e IS
    PORT (
    a,b: IN INTEGER;
    d: OUT BIT_VECTOR(15 DOWNTO 0);
    f: IN BOOLEAN)
    END e;

  2. Mistakes in declaration parts, including: false signal and/or variable bit wide, false signal and/or variable type.

  3. Mistakes in constants, e.g. logic value, integer value, state machine state enumeration names, etc.

    Example:

    Flawed VHDL Code:

    a <= 12;
    b <= TRUE;
    next_state <= state_5

    Corrected VHDL Code:

    a <= 15;
    b <= FALSE;
    next_state <= state_8;

  4. Mistakes in net (identifier) names.

    Example:

    Flawed VHDL Code:

    a <= b + c ;
    z <= x AND y ;

    Corrected VHDL Code:

    a <= b + e ;
    z <= x AND t ;

  5. Misplacement of paranthesis.

    Example:

    Flawed VHDL Code:

    x <= a AND ( b OR c );

    Corrected VHDL Code:

    x <= ( a AND b ) OR c;

  6. Mistake in operators, e.g. logic operators and arithmetic ones.

    Example:

    Flawed VHDL Code:

    x <= a AND b ;
    y <= c - d ;

    Corrected VHDL Code:

    x <= a OR b ;
    y <= c + d ;

  7. Assignment errors, including: deficiency in a necessary assignment, extra existence of an assignment, uncomplete assignment.

    Example:

    Flawed VHDL Code:

    ----
    y <= a AND b;
    z <= a XOR b;

    Corrected VHDL Code:

    x <= a OR b;
    ----
    z <= a XOR b XOR c;

  8. Absence of a conditional (IF-THEN-ELSE and WHEN-CASE) expression.

    Example:

    Flawed VHDL Code:

    next_state <= state_8;

    Corrected VHDL Code:

    IF a='1' THEN
    next_state <= state_8;
    END IF;

  9. Extra conditional control of some expressions that do not need any, though the conditional expression itself must exist to control other expressions.

    Example:

    Flawed VHDL Code:

    output_1 <= FALSE;
    IF a='1' THEN
    next_state <= state_8;
    output_1 <= TRUE;
    END IF;

    Corrected VHDL Code:

    output_1 <= FALSE;
    IF a='1' THEN
    next_state <= state_8;
    END IF;

  10. Deficiency in controlling of some expressions with a conditional expression, though the conditional expression itself exists.

    Example:

    Flawed VHDL Code:

    IF a='1' THEN
    next_state <= state_8;
    END IF;
    output_1 <= TRUE;

    Corrected VHDL Code:

    IF a='1' THEN
    next_state <= state_8;
    output_1 <= TRUE;
    END IF;

  11. Misplacement of an expression in a WHEN-CASE structure.

    Example:

    Flawed VHDL Code:

    CASE a(1 DOWNTO 0) IS
    WHEN "00" => b <= c+1;
    WHEN "01" => b <= c-1;
    WHEN OTHERS => b <= c;
    END CASE;

    Corrected VHDL Code:

    CASE a(1 DOWNTO 0) IS
    WHEN "00" => b <= c+1;
    WHEN "01" => b <= c-1;
    WHEN "10" => b <= c+1;
    WHEN OTHERS => b <= c;
    END CASE;

  12. Mistakes in component instantiation, including: false component name, false port binding or false passed generic parameters.

  13. Mistakes in GENERATE expressions, i.e. extra/inadequate generation of concurrent codes.

  14. Mistakes in function and procedure calls, i.e. false function name, false ports and parameters.

    Example:

    Flawed VHDL Code:

    Corrected VHDL Code:

You are welcome to comment on this survey:

Now, You can send us your answers easily by pressing the following key: