SWITCH LEVEL ANALYSIS

Load Dependent Timing

Resolution
Utilities
Gate model
Simulation

SWITCH LEVEL ANALYSIS - LOAD DEPENDED TIMING

1. Resolution :

Model gates for load dependent timing
Timing depends on capacitance
A resolution function adds all capacitances
Internal Timing depends on total capacitance at output

SWITCH LEVEL ANALYSIS - LOAD DEPENDED TIMING

2. Utilities :

TYPE line IS RECORD logic : wired_qit; load : loading capacitance; END RECORD;

Each port has:
1) A Logical value
2) A Load value
Logical resolution is wired
Load resolution is adding

Utilities

LIBRARY cmos; USE cmos.basic_utilities.ALL; PACKAGE added_utilities IS FUNCTION loading (drivers : capacitance_vector) RETURN capacitance; SUBTYPE loading_capacitance IS loading capacitance; TYPE line IS RECORD logic : wired_qit; load : loading capacitance; END RECORD; END added_utilities; PACKAGE BODY added_utilities IS FUNCTION loading (drivers : capacitance_vector) RETURN capacitance IS VARIABLE load_value : capacitance := 0 ffr; BEGIN FOR i IN drivers'RANGE LOOP load_value := load_value + drivers(i); END LOOP; RETURN load_value; END loading; END added_utilities;

Use most of basic_utilities
Add new types and resolution functions in the
added_utilities

SWITCH LEVEL ANALYSIS - LOAD DEPENDED TIMING

3. Gate Model :

SwitchLevel.LoadDependentTiming.GateModel USE WORK.added_utilities.ALL; -- ENTITY nand_2 IS PORT(in1,in2 : INOUT line; out1 : INOUT line); END nand_2; -- ARCHITECTURE load_dependent OF nand_2 IS CONSTANT pullup : resistance := 15 k_o; CONSTANT pulldown: resistance := 10 k_o; BEGIN in1.load <= 10 ffr; in2.load <= 10 ffr; out1.load <= 2 ffr; in1.logic <= 'Z' ; in2.logic <= 'Z' ; outing : PROCESS(in1.logic , in2.logic) VARIABLE temp_out : qit; BEGIN temp_out := in1.logic NAND in2.logic; IF temp_out = '0' THEN out1.logic <= '0' AFTER 3 * pulldown * out1.load; ELSE IF temp_out = '1' THEN out1.logic <= '1' AFTER 3 * pullup * out1.load; ELSE out1.logic <= temp_out; END IF; END IF; END PROCESS outing; END load_dependent;

out1.load is returned by the resolution function
NAND gate delay depends on total capacitance

SWITCH LEVEL ANALYSIS - LOAD DEPENDED TIMING

4. Simulation :

USE WORK.added_utilities.ALL; ENTITY three_nand_system IS END three_nand_system; -- ARCHITECTURE test OF three_nand_system IS COMPONENT nand_2 PORT(in1,in2 : INOUT line ; out1 : INOUT line); END COMPONENT; SIGNAL a1,b1,b2,b3,q1_out,q2_out,q3_out : line; BEGIN b1.logic <= '1'; b2.logic <= '1'; b3.logic <= '1'; a1.logic <= '0', '1' AFTER 100 NS, '0' AFTER 300 NS, 'Z' AFTER 700 NS, 'X' AFTER 800 NS, '1' AFTER 1000 NS; n1 : nand_2 PORT MAP(a1,b1,q1_out); n2 : nand_2 PORT MAP(q1_out,b2,q2_out); n3 : nand_2 PORT MAP(q1_out,b3,q3_out); END test;
fs a1 b1 b2 b3 q1_out q2_out q3_out 0 (0, 00) (0, 00) (0, 00) (0, 00) (0, 00) (0, 0) (0, 0) 0 (0, 10) (1, 10) (1, 10) (1, 10) (1, 22) (1, 2) (1, 2) 60000 (0, 10) (1, 10) (1, 10) (1, 10) (1, 22) (0, 2) (0, 2) 100000000 (1, 10) (1, 10) (1, 10) (1, 10) (1, 22) (0, 2) (0, 2) 100660000 (1, 10) (1, 10) (1, 10) (1, 10) (0, 22) (0, 2) (0, 2) 100960000 (1, 10) (1, 10) (1, 10) (1, 10) (0, 22) (1, 2) (1, 2) 300000000 (0, 10) (1, 10) (1, 10) (1, 10) (0, 22) (1, 2) (1, 2) 300000105 (0, 10) (1, 10) (1, 10) (1, 10) (1, 22) (1, 2) (1, 2) 299065033 (0, 10) (1, 10) (1, 10) (1, 10) (1, 22) (0, 2) (0, 2) 700000000 (Z, 10) (1, 10) (1, 10) (1, 10) (1, 22) (0, 2) (0, 2) 700660000 (Z, 10) (1, 10) (1, 10) (1, 10) (0, 22) (0, 2) (0, 2) 700960000 (Z, 10) (1, 10) (1, 10) (1, 10) (0, 22) (1, 2) (1, 2) 800000000 (X, 10) (1, 10) (1, 10) (1, 10) (0, 22) (1, 2) (1, 2) 800000000+ (X, 10) (1, 10) (1, 10) (1, 10) (X, 22) (1, 2) (1, 2) 800000000+ (X, 10) (1, 10) (1, 10) (1, 10) (X, 22) (X, 2) (X, 2) 1000000000 (1, 10) (1, 10) (1, 10) (1, 10) (X, 22) (X, 2) (X, 2) 1000660000 (1, 10) (1, 10) (1, 10) (1, 10) (0, 22) (X, 2) (X, 2) 1000960000 (1, 10) (1, 10) (1, 10) (1, 10) (0, 22) (1, 2) (1, 2)

q1_out is the common node between 3 NAND gates
Logic values and capacitances at each node are shown
Timing considers node capacitances

SWITCH LEVEL ANALYSIS

Self Adjusting Switches

Bidirectional Transistor Switches

Theory of Operation

Resolution

Utilities

Gate model

Simulation

SWITCH LEVEL ANALYSIS - SELF-ADJUSTING SWITCHES

1. Bidirectional Transistor Switches :

Transistors operate in two directions
Most designs utilize a transistors in only one direction
Self adjusting finds direction of intended operation

SWITCH LEVEL ANALYSIS - SELF-ADJUSTING SWITCHES

2. Theory of Operation :

Sources identify themselves by pushing values in the circuit
Values go through series transistors
Values WAIT at intersections (np) before they are resolved
Models for np-intersection, sources, and gates

SWITCH LEVEL ANALYSIS - SELF-ADJUSTING SWITCHES

3. Resolution :

( 'T', -- Transitional value for all Source and Drain 'G', -- Initial value of all transistor Gate terminals U0, -- Unknown, direction is known transmits 0 U1, -- Unknown, direction is known transmits 1 'U', -- Unknown, direction is known transmits 0 or 1 '0', -- Low '1', -- High 'Z', -- High Impedance 'X', -- Conflict 'W' -- Node is in the WAIT state )

Ten value logic system
All nodes are initially at T' value
U values are assigned when direction is known

Resolution

( -- 'T','G', U0, U1,'U','0','1','Z','X','W' -- --------------------------------------- 'T' : ('T','G', U0, U1,'U','0','1','Z','X','W'), 'G' : ('G','G','G','G','G','0','1','Z','X','W'), UO : ( U0,'G', U0,'U', U0,'0','1','Z','X','W'), U1 : ( U1,'G','U', U1, U1,'0','1','Z','X','W'), 'U' : ('U','G','U','U','U','0','1','Z','X','W'), '0' : ('0','0','0','0','0','0','X','0','X','W'), '1' : ('1','1','1','1','1','X','1','1','X','W'), 'Z' : ('Z','Z','Z','Z','Z','0','1','Z','X','W'), 'X' : ('X','X','X','X','X','X','X','X','X','W'), 'W' : ('W','W','W','W','W','W','W','W','W','W'));

Transitional is replaced by and value at that node
Gates do not propagate values until a real logic value arrives

Resolution

FUNCTION t_resolve (drivers : t_values) RETURN t_value IS TYPE t_value_2d IS ARRAY (t_value, t_value) OF t_value; CONSTANT t_table : t_value_2d := ( -- 'T','G', U0, U1,'U','0','1','Z','X','W' -- --------------------------------------- ('T','G', U0, U1,'U','0','1','Z','X','W'), --'T' ('G','G','G','G','G','0','1','Z','X','W'), --'G' ( U0,'G', U0,'U', U0,'0','1','Z','X','W'), -- U0 ( U1,'G','U', U1, U1,'0','1','Z','X','W'), -- U1 ('U','G','U','U','U','0','1','Z','X','W'), --'U' ('0','0','0','0','0','0','X','0','X','W'), --'0' ('1','1','1','1','1','X','1','1','X','W'), --'1' ('Z','Z','Z','Z','Z','0','1','Z','X','W'), --'Z' ('X','X','X','X','X','X','X','X','X','W'), --'X' ('W','W','W','W','W','W','W','W','W','W')); --'W' VARIABLE accumulate : t_value; VARIABLE count : INTEGER; BEGIN count := 0; FOR i IN drivers'RANGE LOOP accumulate := t_table (accumulate, drivers(i)); count := count + 1; END LOOP; IF count > 2 AND accumulate = 'T' THEN RETURN 'W'; ELSE RETURN accumulate; END IF; END t_resolve;

Wait when more than one line are connected

SWITCH LEVEL ANALYSIS - SELF-ADJUSTING SWITCHES

4. Utilities (Components)

USE WORK.t_utilities.ALL; ENTITY ground IS PORT (gnd : OUT t_bit := 'T'); END ground; -- ARCHITECTURE triggering OF ground IS BEGIN gnd <= '0'; END triggering; -- USE WORK.t_utilities.ALL; ENTITY supply IS PORT (vdd : OUT t_bit := 'T'); END supply; -- ARCHITECTURE triggering OF supply IS BEGIN vdd <= '1'; END triggering; -- USE WORK.t_utilities.ALL; ENTITY cap IS GENERIC (cap_val : capacitance := 0 ffr); PORT (line : OUT t_bit := 'T'); END cap; -- ARCHITECTURE loading OF cap IS BEGIN END loading;

GND injects 0' at time 0
SUPPLY injets 1' at time 0
CAP sits on line and provides capacitance value

SWITCH LEVEL ANALYSIS - SELF-ADJUSTING SWITCHES

5. Gate Model :

USE WORK.t_utilities.ALL; USE WORK.t_parameters.ALL; ENTITY nmos IS GENERIC (l : lambda := 2; w : lambda := 6); PORT (source : INOUT t_bit := 'T'; gate : INOUT t_bit := 'G'; drain : INOUT t_bit := 'T' ); END nmos; -- ARCHITECTURE self_adjusting OF nmos IS SIGNAL effective_gate : t_bit; CONSTANT propagation : TIME := l**2 * unit_n_res * unit_gate_cap * 2; BEGIN effective_gate <= '0' AFTER ngate_discharge WHEN gate = 'Z' ELSE gate; PROCESS TYPE logic_flow IS (und, d2s, s2d); VARIABLE direction : logic_flow; BEGIN IF direction = und THEN . . . Find Direction . . . ELSIF direction = s2d THEN . . . Operate only if event on source . . . ELSE -- direction = d2s . . . Operate only if event on drain . . . END IF; WAIT ON effective_gate, source, drain; END PROCESS; END self_adjusting;

Three modes of operation for each transistor
Direction is undecided, s2, or p2s

Gate Model

ARCHITECTURE self_adjusting OF nmos IS SIGNAL effective_gate : t_bit; CONSTANT propagation : TIME := l**2 * unit_n_res * unit_gate_cap * 2; BEGIN effective_gate <= '0' AFTER ngate_discharge WHEN gate = 'Z' ELSE gate; PROCESS TYPE logic_flow IS (und, d2s, s2d); VARIABLE direction : logic_flow; BEGIN IF direction = und THEN IF source'EVENT AND source /= 'G' AND source /= U1 THEN direction := s2d; IF drain = 'W' THEN WAIT FOR 1 FS; END IF; drain <= U0; ELSIF drain'EVENT AND drain /= 'G' AND drain /= U1 THEN direction := d2s; IF source = 'W' THEN WAIT FOR 1 FS; END IF; source <= U0; END IF; ELSIF direction = s2d THEN . . . Operate only if event on source . . . ELSE -- direction = d2s . . . Operate only if event on drain . . . END IF; WAIT ON effective_gate, source, drain; END PROCESS; END self_adjusting;

Decide on direction based on non-WAIT events on S or D
Wait for all interconnecting wires to get their values

Gate Model

ARCHITECTURE self_adjusting OF nmos IS SIGNAL effective_gate : t_bit; CONSTANT propagation : TIME := l**2 * unit_n_res * unit_gate_cap * 2; BEGIN effective_gate <= '0' AFTER ngate_discharge WHEN gate = 'Z' ELSE gate; PROCESS TYPE logic_flow IS (und, d2s, s2d); VARIABLE direction : logic_flow; BEGIN IF direction = und THEN . . . Find Direction . . . ELSIF direction = s2d THEN IF effective_gate'EVENT OR source'EVENT THEN CASE effective_gate IS WHEN '0' => drain <= 'Z'; WHEN '1' => drain <= source AFTER propagation; WHEN OTHERS => drain <= effective_gate; END CASE; END IF; ELSE -- direction = d2s . . . Operate only if event on drain . . . END IF; WAIT ON effective_gate, source, drain; END PROCESS; END self_adjusting;

Propagate source values if this is the direction of operation
Consider Gate values

Gate Model

ARCHITECTURE self_adjusting OF nmos IS SIGNAL effective_gate : t_bit; CONSTANT propagation : TIME := l**2 * unit_n_res * unit_gate_cap * 2; BEGIN effective_gate <= '0' AFTER ngate_discharge WHEN gate = 'Z' ELSE gate; PROCESS TYPE logic_flow IS (und, d2s, s2d); VARIABLE direction : logic_flow; BEGIN IF direction = und THEN . . . Find Direction . . . ELSIF direction = s2d THEN . . . Operate only if event on source . . . ELSE -- direction = d2s IF effective_gate'EVENT OR drain'EVENT THEN CASE effective_gate IS WHEN '0' => source <= 'Z'; WHEN '1' => source <= drain AFTER propagation; WHEN OTHERS => source <= effective_gate; END CASE; END IF; END IF; WAIT ON effective_gate, source, drain; END PROCESS; END self_adjusting;

Propagate drain values if this is the direction of operation
Consider Gate values

Gate Model (Load Dependency)

TYPE t_bit IS RECORD logic : t_logic; cap : t_cap; END RECORD;

USE WORK.t_utilities.ALL; ENTITY ground IS PORT (gnd : OUT t_bit := ('T', 0 ffr)); END ground; -- ARCHITECTURE triggering OF ground IS BEGIN gnd <= ('0', 0 ffr); END triggering; -- USE WORK.t_utilities.ALL; ENTITY supply IS PORT (vdd : OUT t_bit := ('T', 0 ffr)); END supply; -- ARCHITECTURE triggering OF supply IS BEGIN vdd <= ('1', 0 ffr); END triggering; -- USE WORK.t_utilities.ALL; ENTITY cap IS GENERIC (cap_val : capacitance := 0 ffr); PORT (line : OUT t_bit := ('T', 0 ffr)); END cap; -- ARCHITECTURE loading OF cap IS BEGIN line.cap <= cap_val; END loading;

To consider load dependency, use cap in each line record
Assign composite values

GateModel (Load Dependency)

ENTITY nmos IS GENERIC (l : lambda := 2; w : lambda := 6); PORT (source : INOUT t_bit := ('T', 0 ffr); gate : INOUT t_bit := ('G', l*w*unit_gate_cap); drain : INOUT t_bit := ('T', 0 ffr) ); END nmos; -- ARCHITECTURE self_adjusting OF nmos IS SIGNAL effective_gate : t_logic; BEGIN . . . PROCESS TYPE logic_flow IS (und, d2s, s2d); VARIABLE direction : logic_flow; BEGIN . . . ELSIF direction = s2d THEN IF effective_gate'EVENT OR source.logic'EVENT THEN CASE effective_gate IS WHEN '0' => drain.logic <= 'Z'; source.cap <= 0 ffr; WAIT ON drain.logic'TRANSACTION; WHEN '1' => drain.logic <= source.logic AFTER (l*unit_n_res/w)*drain.cap; source.cap <= drain.cap AFTER (l*unit_n_res/w)*drain.cap; WAIT ON drain.logic'TRANSACTION; WHEN OTHERS => drain.logic <= effective_gate; source.cap <= 0 ffr; WAIT ON drain.logic'TRANSACTION; END CASE; END IF; . . . WAIT ON effective_gate, source.logic, drain.logic; END PROCESS; END self_adjusting;

Load capacitance and logic move in opposite directions

SWITCH LEVEL ANALYSIS - SELF-ADJUSTING SWITCHES

6. Simulation :

A total of 10 transistors
PMOS models are like NMOS except for gate polarity

Simulation

LIBRARY tgate; USE tgate.t_utilities.ALL; USE tgate.t_components.ALL; ENTITY latch IS PORT (i1, c1, o1 : INOUT t_bit); END latch; -- ARCHITECTURE tgate_based OF latch IS SIGNAL gnd, vdd : t_bit; SIGNAL ii, ix, cb : t_bit; BEGIN g1: ground PORT MAP (gnd); s1: supply PORT MAP (vdd); t1 : nmos GENERIC MAP (2, 6) PORT MAP (gnd, c1, cb); t2 : pmos GENERIC MAP (2, 6) PORT MAP (cb, c1, vdd); t3 : nmos GENERIC MAP (2, 6) PORT MAP (i1, c1, ii); t4 : pmos GENERIC MAP (2, 6) PORT MAP (i1, cb, ii); t5 : nmos GENERIC MAP (2, 6) PORT MAP (gnd, ii, ix); t6 : pmos GENERIC MAP (2, 6) PORT MAP (vdd, ii, ix); t7 : nmos GENERIC MAP (2, 6) PORT MAP (gnd, ix, o1); t8 : pmos GENERIC MAP (2, 6) PORT MAP (vdd, ix, o1); t9 : nmos GENERIC MAP (2, 6) PORT MAP (o1, cb, ii); t10: pmos GENERIC MAP (2, 6) PORT MAP (o1, c1, ii); c01 : cap GENERIC MAP (6 ffr) PORT MAP (o1); c02 : cap GENERIC MAP (5 ffr) PORT MAP (ii); c03 : cap GENERIC MAP (3 ffr) PORT MAP (ix); c04 : cap GENERIC MAP (4 ffr) PORT MAP (cb); c05 : cap GENERIC MAP (3 ffr) PORT MAP (i1); c06 : cap GENERIC MAP (3 ffr) PORT MAP (c1); putbit (i1, "i1_vals.bit"); putbit (c1, "c1_vals.bit"); END tgate_based;

A netlist of transistors, capacitors and Vdd and Gnd

Simulation

SwitchLevel.SelfAdjustingSwitches.Simulation ps delta i1 c1 x_x(44) o1 0 +0 (W, 0) (G, 96) (G, 48) (W, 0) 0 +1 (U, 5) (G, 100) (G, 61) (W, 8) 1 +1 (U, 5) (G, 100) (G, 61) (U, 8) 200000 +0 (1, 5) (1, 100) (G, 61) (U, 8) 200000 +2 (1, 5) (1, 100) (Z, 61) (U, 8) 200228 +0 (1, 66) (1, 100) (1, 61) (U, 8) 200324 +0 (1, 66) (1, 100) (1, 61) (1, 8) 800000 +0 (1, 66) (0, 100) (1, 61) (1, 8) 800130 +2 (1, 5) (0, 100) (Z, 61) (1, 8) 800147 +0 (1, 5) (0, 100) (1, 61) (1, 69) 800222 +0 (1, 5) (0, 100) (1, 61) (1, 130) 1200000 +0 (0, 5) (0, 100) (1, 61) (1, 130) 1400000 +0 (0, 5) (1, 100) (1, 61) (1, 130) 1400000 +2 (0, 5) (1, 100) (1, 61) (1, 69) 1400081 +2 (0, 5) (1, 100) (Z, 61) (1, 8) 1400092 +0 (0, 66) (1, 100) (0, 61) (1, 8) 1400215 +2 (0, 66) (1, 100) (0, 61) (Z, 8) 1400227 +0 (0, 66) (1, 100) (0, 61) (0, 8) 1400228 +0 (0, 127) (1, 100) (0, 61) (0, 8) 2000000 +0 (0, 127) (0, 100) (0, 61) (0, 8) 2000000 +2 (0, 66) (0, 100) (0, 61) (0, 8) 2000130 +2 (0, 5) (0, 100) (Z, 61) (0, 8) 2000147 +0 (0, 5) (0, 100) (0, 61) (0, 69) 2000222 +0 (0, 5) (0, 100) (0, 61) (0, 130) 2400000 +0 (1, 5) (0, 100) (0, 61) (0, 130) 2600000 +0 (1, 5) (1, 100) (0, 61) (0, 130) 2600000 +2 (1, 5) (1, 100) (0, 61) (0, 69) 2600081 +2 (1, 5) (1, 100) (Z, 61) (0, 8) 2600092 +0 (1, 66) (1, 100) (1, 61) (0, 8) 2600169 +2 (1, 66) (1, 100) (1, 61) (Z, 8) 2600188 +0 (1, 66) (1, 100) (1, 61) (1, 8) 2600228 +0 (1, 127) (1, 100) (1, 61) (1, 8)

Simulation result shows logic operatios
Node capacitances depend on switches being On or Off
Output cap=8, Gate input=69, Gate output=61, 61+69=130