STRUCTURAL ANALYSIS












STRUCTURAL ANALYSIS- COOB MODELING




1. COOB :



OR: Cout = 1 - (1 - Cin1) * (1 - Cin2) = 0.625
Oin1 = Oout * (1 - Cin2) = 0.5
Oin2 = Oout * (1 - Cin1) = 0.75

AND: Cout = Cin1 * Cin2 = 0.25
Oin1 = Oout * Cin2 = 0.25
Oin2 = Oout * Cin1 = 0.25





  • COOB for testability analysis
  • Testable design based on COOB values
  • Modular calculations, based on PI CO values










STRUCTURAL ANALYSIS- COOB MODELING




2. General Strategy :





  • PIs start by assigning CO to their connecting gates
  • POs Wait or CO values and then assign OB values
  • Gates calculate CO values on the first pass and save
  • Gates calculate OB values on the second pass
  • Gate OB values depend on their CO values
















STRUCTURAL ANALYSIS- COOB MODELING




3. Gate IO Structure :





  • Each port is INOUT for passing info in both directions
  • COs move from PI to PO, use co_cal resolution function
  • OBs move from PO to PI, use ob_cal resolution function
  • ALL CO and OB initial values are none







Gate IO Structure 



    
PACKAGE  control_observe  IS
  CONSTANT none  : REAL := -1.0;
  TYPE  real_vector IS  ARRAY ( NATURAL RANGE <> ) OF REAL;
  FUNCTION  co_cal ( drivers : real_vector ) RETURN real; 
  SUBTYPE   co_real  IS  co_cal REAL;
  FUNCTION  ob_cal ( drivers : real_vector ) RETURN real;
  SUBTYPE   ob_real  IS  ob_cal REAL;
  --
  TYPE con_ob IS RECORD
    control : co_real;
    observe : ob_real;
  END RECORD;
  --
END control_observe;

PACKAGE BODY control_observe IS
  FUNCTION  co_cal ( drivers : real_vector ) RETURN real IS
  BEGIN
     FOR i IN drivers'RANGE LOOP      
       IF drivers(i) /= none THEN    
         RETURN drivers(i);
       END IF;
     END LOOP;
     RETURN  none;   
  END co_cal;
  --
  FUNCTION  ob_cal ( drivers : real_vector ) RETURN real IS  
    VARIABLE none_count : INTEGER := 0;  
    VARIABLE temp       : REAL := -1.0;  
  BEGIN
    . . .
    FOR i IN drivers'RANGE LOOP
      IF drivers(i) > temp THEN
        temp := drivers(i);
      END IF;
    END LOOP;    
    RETURN temp;
  END ob_cal;
END control_observe;


  • co_cal resolution function resolves to a none none value
  • ob_cal resolution function resolves to largest OB value










STRUCTURAL ANALYSIS- COOB MODELING




4. Use of Real Time : 


    
PACKAGE  control_observe  IS

  CONSTANT repeat : INTEGER := 3;

  TYPE pi_prob_table IS ARRAY (1 TO repeat) OF REAL;
  CONSTANT pi_prob : pi_prob_table := ( 0.5, 0.75, 0.25);  
  
  CONSTANT filename : STRING := "CON_OBS.TXT";    
  TYPE gate_record IS ARRAY (1 TO 3) OF con_ob;
  TYPE keep_record IS ARRAY (1 TO repeat) OF gate_record;
END control_observe;


  • Delta time to forward CO values
  • OB values propagate through gates at delta time distances
  • Three sets of COOB calculations are separated by NS real time
  • Gates are delayed by their id values before writing COOB values to a single file










STRUCTURAL ANALYSIS- COOB MODELING




5. COOB Gates : 



    
ENTITY or2_oc IS
  GENERIC ( gate_id    : NATURAL );  PORT    ( i1, i2, o1 : INOUT con_ob := init );
END or2_oc;
--
ARCHITECTURE testability OF or2_oc IS
BEGIN
  PROCESS
    VARIABLE temp : gate_record := (others => init);
    VARIABLE history : keep_record;
    VARIABLE i : INTEGER := 1; 
  BEGIN
    WAIT UNTIL i1.control /= none AND i2.control /= none;
    temp(1).control := i1.control;   temp(2).control := i2.control;
    temp(3).control := 
temp(1).control + temp(2).control - (temp(1).control * temp(2).control);
    o1.control <= temp(3).control;
    WAIT UNTIL o1.observe /= none;
        temp(3).observe := o1.observe;  
    temp(1).observe := o1.observe * (1.0 - i2.control);  i1.observe <= temp(1).observe;
    temp(2).observe := o1.observe * (1.0 - i1.control);  i2.observe <= temp(2).observe;

    history(i) := temp;
    i := i+1;
    WAIT FOR 0 ns;  
    IF i <= repeat THEN
      --- initialization
      WAIT FOR 1 ns;
      i1 <= init;      i2 <= init;      o1 <= init;
      WAIT FOR 1 ns;
    ELSE
      WAIT FOR gate_id*1 NS;
      write_to_file (gate_id, "OR", history);
      WAIT;
    END IF;
  END PROCESS;
END testability;


  • WAIT for separating calculations, reporting, and restarting
  • All gates are synchronized within 1 NS times
  • Gates report their and 3 sets of COOB values










STRUCTURAL ANALYSIS- COOB MODELING




6. COOB_PIO : 



    
ENTITY pi_oc IS
  GENERIC ( gate_id : NATURAL );
  PORT    ( o1      : INOUT con_ob := init );
END pi_oc;
--
ARCHITECTURE testability OF pi_oc IS
BEGIN
  PROCESS
    VARIABLE temp : gate_record := (others => init);   
    VARIABLE history : keep_record;
    VARIABLE i : INTEGER := 1; 
  BEGIN
    o1.control <=  pi_prob(i);
    temp(3).control := pi_prob(i);
    WAIT UNTIL o1.observe /= none;
    temp(3).observe := o1.observe;
    history(i) := temp;
    i := i+1;
    IF i <= repeat THEN
      --- initialization
      WAIT FOR 1 ns;
      o1 <= init;
      WAIT FOR 1 ns;
    ELSE
      WAIT FOR gate_id*1 NS;
      write_to_file(gate_id, "PI", history);
      WAIT;
    END IF;
  END PROCESS;
END testability;


  • For each signal probability at a PI, assign to output,
  • Wait until OB reaches back, Pick a next signal probability,
  • Continue until all values are consumed, Report OB,
  • Quit







COOB PIO 


    
ENTITY po_oc IS
  GENERIC ( gate_id : NATURAL );  PORT    ( i1      : INOUT con_ob := init );
END po_oc;
--
ARCHITECTURE testability OF po_oc IS
BEGIN
  PROCESS
    VARIABLE temp : gate_record := (others => init);
    VARIABLE history : keep_record;
    VARIABLE i : INTEGER := 1; 
  BEGIN
    WAIT UNTIL i1.control /= none ;
    temp(1).control := i1.control;
    i1.observe <= 1.0;
    temp(1).observe := 1.0;
    WAIT FOR 0 ns;
    history(i) := temp;
    i := i+1;
    IF i <= repeat THEN
      --- initialization
      WAIT FOR 1 ns;
      i1 <= init;
      WAIT FOR 1 ns;
    ELSE
      WAIT FOR gate_id*1 NS;
      write_to_file(gate_id, "PO", history);
      WAIT;
    END IF;
  END PROCESS;
END testability;


  • PO model waits for CO values to arrive
  • OB value of 1.0 will be assigned back to the output gate
  • Values will be saved and then all reported










STRUCTURAL ANALYSIS- COOB MODELING




7. Example Run : 



    
ENTITY c2 IS END c2;

ARCHITECTURE oc_gates OF c2 IS
  SIGNAL i : con_ob_vector(1 TO 9);
BEGIN
  g1 : pi_s GENERIC MAP (1) PORT MAP (i(1));
  g2 : pi_s GENERIC MAP (2) PORT MAP (i(2));
  g3 : pi_s GENERIC MAP (3) PORT MAP (i(3));
  g4 : pi_s GENERIC MAP (4) PORT MAP (i(4));
  g5 : pi_s GENERIC MAP (5) PORT MAP (i(5));
  g6 : n GENERIC MAP (6) PORT MAP (i(2),i(3),i(6));
  g7 : n GENERIC MAP (7) PORT MAP (i(4),i(5),i(8));   
  g8 : a GENERIC MAP (8) PORT MAP (i(1),i(6),i(7));
  g9 : o GENERIC MAP (9) PORT MAP (i(7),i(8),i(9));
  g10: po_s GENERIC MAP (10) PORT MAP (i(8)); 
  g11 : po_s GENERIC MAP (11) PORT MAP (i(9)); 
END oc_gates;


  • A testbench for COOB instantiates gates and PIO
  • Gates generate the report of COOB values







Example Run 


    
PI no. 0001 reporting :
 For iteration no. 0001
-1.000000e+000 ; controlability of input 1   
-1.000000e+000 ; observeability of input 1   
-1.000000e+000 ; controlability of input 2   
-1.000000e+000 ; observeability of input 2   
 5.000000e-001 ; controlability of output    
 1.875000e-001 ; observeability of output   
. . 
NAND no. 0006 reporting :
 For iteration no. 0001
 5.000000e-001 ; controlability of input 1   
 6.250000e-002 ; observeability of input 1   
 5.000000e-001 ; controlability of input 2   
 6.250000e-002 ; observeability of input 2   
 7.500000e-001 ; controlability of output    
 1.250000e-001 ; observeability of output   
.  . .
OR no. 0009 reporting :
 For iteration no. 0001
 3.750000e-001 ; controlability of input 1   
 2.500000e-001 ; observeability of input 1   
 7.500000e-001 ; controlability of input 2   
 6.250000e-001 ; observeability of input 2   
 8.437500e-001 ; controlability of output    
 1.000000e+000 ; observeability of output   
. . .
PO no. 0010 reporting :
 For iteration no. 0001
 7.500000e-001 ; controlability of input 1   
 1.000000e+000 ; observeability of input 1   
-1.000000e+000 ; controlability of input 2   
-1.000000e+000 ; observeability of input 2   
-1.000000e+000 ; controlability of output    
-1.000000e+000 ; observeability of output


  • PIs have no inputs, POs have no outputs
  • All other gates report values on all their ports













STRUCTURAL ANALYSIS












STRUCTURAL ANALYSIS- LOGIC CONES




1. Cone Definition :





  • Partition based on output
  • Useful in test generation, fault simulation,
  • VHDL models work based on time of output activities

STRUCTURAL ANALYSIS- LOGIC CONES




2. Theory of Operation :





  • Bidirectional operation, INOUT IO lines
  • Sensitive to all IO events
  • Propagate all logic simulation results in Delta times
  • Disable output sensitivities until complete propagation of simulation logic values
  • Not sensitive to input values, while in cone identification mode (no forwarding for gates and fanouts)
  • Real simulation time of output activity identifies gate cone










STRUCTURAL ANALYSIS- LOGIC CONES




3. Utilities : 



    
PACKAGE dg_utils IS
    TYPE cbit IS ('N', '0', '1', 'P');
    TYPE cbit_2d IS ARRAY (cbit,cbit) OF cbit;
    TYPE cbit_1d IS ARRAY (cbit) OF cbit;
    TYPE cbit_vector IS ARRAY (NATURAL RANGE <>) OF cbit;  
    
    FUNCTION resolve (a:cbit_vector) RETURN cbit;
    SUBTYPE node IS resolve cbit;
    FUNCTION "NAND" (a,b :cbit) RETURN cbit;
    FUNCTION "AND" (a,b :cbit) RETURN cbit;
    FUNCTION "NOT" (a :cbit) RETURN cbit;
    PROCEDURE reporting (CONSTANT i : INTEGER);
END dg_utils;


  • Type cbit is used for logic simulation and cone identification
  • Utilities include resolution functions, overloading logic operations, and a reporting procedure







Utilities 

    
PACKAGE BODY dg_utils IS
    FUNCTION "NAND" (a,b: cbit) RETURN cbit IS
        VARIABLE result :cbit;
    BEGIN
        IF a='1' AND b='1' THEN
            result :='0';
        ELSE
            result :='1';
        END IF;
        RETURN result;
    END "NAND";
    FUNCTION "NOT" (a: cbit) RETURN cbit IS . . .
    . . . 
    FUNCTION "AND" (a,b: cbit) RETURN cbit IS . . .
    . . . 
    FUNCTION resolve (a :cbit_vector) RETURN cbit IS  
        VARIABLE result : cbit := 'N';
    BEGIN
        FOR i IN a'RANGE LOOP
            IF a(i) = 'P' THEN
                result := 'P';
                EXIT;
            ELSIF a(i) = '1' THEN
                result := '1';
            ELSIF a(i) = '0' THEN
                result := '0';
            END IF;
        END LOOP;
        RETURN result;
    END resolve;
    . . .
END dg_utils;


  • Overloading NAND and resolve function







Utilities 


    
PACKAGE BODY dg_utils IS
    . . . 
PROCEDURE reporting (CONSTANT i : INTEGER) IS
      FILE cones : TEXT OPEN APPEND_MODE IS "cone.dat";
      VARIABLE l : LINE;
      CONSTANT s1 : STRING := "Gate number: ";
      CONSTANT s2 : STRING := " is part of cone triggered at: ";  
    BEGIN
      WRITE (l, s1);
      WRITE (l, i);
      WRITE (l, s2);
      WRITE (l, NOW, RIGHT, 8, NS);
      WRITELINE (cones, l);
    END;
END dg_utils;


  • Reporting gate numbers and cone
  • NOW indicates the cone that a gate belongs to










STRUCTURAL ANALYSIS- LOGIC CONES




4. Gate Models : 


    
ENTITY nand2 IS
    GENERIC (id :INTEGER; tplh, tphl :TIME);
    PORT (a,b,c :INOUT node);
END nand2;

ARCHITECTURE cone OF nand2 IS
BEGIN
  a <= 'N';
  b <= 'N';
  c <= 'N';
  PROCESS
  BEGIN
    IF (a'EVENT OR b'EVENT) AND (a /= 'P') AND (b /= 'P') THEN 
      c <= a NAND b;
      WAIT FOR id * 1 FS;
    ELSIF c'EVENT AND c = 'P' THEN
      a <= 'P', 'N' AFTER 1 FS;
      b <= 'P', 'N' AFTER 1 FS;
      WAIT FOR id * 1 FS;
      reporting (id);
    END IF;
    WAIT ON a, b, c;
  END PROCESS;
END cone;


  • Forward logic simulation
  • WAIT id*1 FS for output events to pass through
  • P' comes from the output and identifies a cone
  • When output events occur, pass them to the inputs and report the gate id at the coarse time of the output event
  • Separate reporting to file by id*1FS to protect against concurrent writing
  • All values become Neutral after cone identification










STRUCTURAL ANALYSIS- LOGIC CONES




5. Test Bench : 



    
USE WORK.dg_utils.ALL;
ENTITY fulladder IS
    PORT (a, b, c, s, co : INOUT node);
END fulladder;

ARCHITECTURE dg_nand OF fulladder IS
  COMPONENT nand2 PORT (a,b,c :INOUT node); END COMPONENT;
  SIGNAL im1,im2,im3,im4,im5,im6,im7,im8,im9 : node;
  FOR ALL : nand2 
    USE ENTITY WORK.nand2(cone) GENERIC MAP (0, 4 NS, 5 NS);
BEGIN
  g01: nand2 PORT MAP (a,b,im1);
  g02: nand2 PORT MAP (a,im1,im2);
  g03: nand2 PORT MAP (im1,b,im3);
  g04: nand2 PORT MAP (im2,im3,im4);
  g05: nand2 PORT MAP (im4,c,im5);
  g06: nand2 PORT MAP (im4,im5,im6);  
  g07: nand2 PORT MAP (im5,c,im7);
  g08: nand2 PORT MAP (im6,im7,s);
  g09: nand2 PORT MAP (a,b,im8);
  g10: nand2 PORT MAP (im4,c,im9);
  g11: nand2 PORT MAP (im9,im8,co);
END dg_nand;


  • Instantiate gates of a full-adder
  • All ports are INOUT







Test Bench 


    
USE WORK.dg_utils.ALL;
CONFIGURATION test1 OF fulladder IS
    FOR dg_nand
        FOR g01:nand2            GENERIC MAP (id => 1);        END FOR;
        FOR g02:nand2            GENERIC MAP (id => 2);        END FOR;
        FOR g03:nand2            GENERIC MAP (id => 3);        END FOR;
        FOR g04:nand2            GENERIC MAP (id => 4);        END FOR;
        FOR g05:nand2            GENERIC MAP (id => 5);        END FOR;
        FOR g06:nand2            GENERIC MAP (id => 6);        END FOR;
        FOR g07:nand2            GENERIC MAP (id => 7);        END FOR;
        FOR g08:nand2            GENERIC MAP (id => 8);        END FOR;
        FOR g09:nand2            GENERIC MAP (id => 9);        END FOR;
        FOR g10:nand2            GENERIC MAP (id => 10);       END FOR;
        FOR g11:nand2            GENERIC MAP (id => 11);       END FOR;
    END FOR;
END test1;


  • Configure for unique gate identification
  • Could use VHDL'93 Instance Name







Test Bench 


    
USE WORK.dg_utils.ALL;
ENTITY cone_test_bench IS
END cone_test_bench;

ARCHITECTURE input_output OF cone_test_bench IS
    COMPONENT fulladder PORT (a, b, c, s, co :INOUT node);
    END COMPONENT;
    FOR d1 : fulladder USE CONFIGURATION WORK.test1;
    SIGNAL a, b, c, s, co : node;

BEGIN
    d1: fulladder PORT MAP (a,b,c, s, co);
    a1: a <= '0' AFTER 0100 NS, '1' AFTER 0200 NS, '0' AFTER 0300 NS,
             '1' AFTER 0400 NS, '0' AFTER 0500 NS, '1' AFTER 0600 NS,
             'N' AFTER 2100 NS,
             '0' AFTER 3000 NS, '1' AFTER 3100 NS,
             'N' AFTER 3500 NS;

    b1: b <= '0' AFTER 0200 NS, '1' AFTER 0400 NS, '0' AFTER 0600 NS,
             '1' AFTER 0800 NS, '0' AFTER 1000 NS, '1' AFTER 1200 NS,
             'N' AFTER 2100 NS,
             '0' AFTER 3000 NS, '1' AFTER 3200 NS,
             'N' AFTER 3500 NS;

    c1: c <= '0' AFTER 0300 NS, '1' AFTER 0600 NS, '0' AFTER 0900 NS,
             '1' AFTER 1200 NS, '0' AFTER 1500 NS, '1' AFTER 1800 NS,   
             'N' AFTER 2100 NS,
             '0' AFTER 3000 NS, '1' AFTER 3300 NS,
             'N' AFTER 3500 NS;

    s  <= 'N', 'P' AFTER 2200 NS, 'N' AFTER 2200.1 NS;
    co <= 'N', 'P' AFTER 3600 NS, 'N' AFTER 3600.1 NS;
END input_output;


  • Assign input logic values, Neutralize inputs for output cones
  • Output s is identified at 2200 NS and co at 3600 NS










STRUCTURAL ANALYSIS- LOGIC CONES




6. Simulation : 



    
--LIST FILE:
         fs  delta a b c s co 
          0     +0 N N N N  N 
  100000000     +0 0 N N N  N 
  100000000     +2 0 N N N  1 
  100000000     +4 0 N N 1  1 
  200000000     +0 1 0 N 1  1 
  300000000     +0 0 0 0 1  1 
  400000000     +0 1 1 0 1  1 
  500000000     +0 0 1 0 1  1 
  500000000     +2 0 1 0 1  0 
  600000000     +0 1 0 1 1  0 
  600000000     +2 1 0 1 1  1 
  800000000     +0 1 1 1 1  1 
  900000000     +0 1 1 0 1  1 
  900000000     +2 1 1 0 0  1 
 1000000000     +0 1 0 0 0  1 
 1000000000     +2 1 0 0 0  0 
 1200000000     +0 1 1 1 0  0 
 1200000000     +2 1 1 1 1  1 
 1500000000     +0 1 1 0 1  1 
 1800000000     +0 1 1 1 1  1 
 2100000000     +0 N N N 1  1 
 2100000000     +2 N N N 0  0 
 2200000000     +0 N N N P  0 
 2200000000     +2 N N P P  0 
 2200000000     +4 P P P P  0 
 2200000001     +0 N N N P  0 
 2200100098     +0 N N N 0  0   
 3000000000     +0 0 0 0 0  0 
 3100000000     +0 1 0 0 0  0 
 3200000000     +0 1 1 0 0  0 
 3200000000     +2 1 1 0 0  1 
 3300000000     +0 1 1 1 0  1 
 3300000000     +2 1 1 1 1  1 
 3500000000     +0 N N N 1  1 
 3500000000     +2 N N N 0  0 
 3600000000     +0 N N N 0  P 
 3600000000     +2 P P P 0  P 
 3600000001     +0 N N N 0  P 
 3600100098     +0 N N N 0  0


  • Simulation report file shows gate logic values







Simulation 


    
--REPORT FILE:
Gate number:  1 is part of cone triggered at: 2200.000001 ns
Gate number:  2 is part of cone triggered at: 2200.000002 ns
Gate number:  3 is part of cone triggered at: 2200.000003 ns
Gate number:  4 is part of cone triggered at: 2200.000004 ns
Gate number:  5 is part of cone triggered at: 2200.000005 ns
Gate number:  6 is part of cone triggered at: 2200.000006 ns
Gate number:  7 is part of cone triggered at: 2200.000007 ns
Gate number:  8 is part of cone triggered at: 2200.000008 ns
Gate number:  1 is part of cone triggered at: 3600.000001 ns
Gate number:  2 is part of cone triggered at: 3600.000002 ns
Gate number:  3 is part of cone triggered at: 3600.000003 ns
Gate number:  4 is part of cone triggered at: 3600.000004 ns
Gate number:  9 is part of cone triggered at: 3600.000009 ns
Gate number: 10 is part of cone triggered at: 3600.000010 ns
Gate number: 11 is part of cone triggered at: 3600.000011 ns


  • cone.dat file contains partitioning information
  • Gate 5 is part of s cone activated at 2200 NS
  • Gate 9 is part of co cone activated at 3600 NS
  • Gate 3 is part of both s and co cones