·

This tutorial presents techniques for utilizing many unexplored capabilities of VHDL. The focus is on those special features of the language that can be used to model hardware for applications that are not normally expected from a hardware description language. We will see how a VHDL simulation run can generate results such as circuit partitioning, testability analysis, switch level timing, and test vectors.

·

This presentation focuses on VHDL as a modeling language. The use of VHDL simulation tools for purposes other than simulation and verification of design will be described. Using VHDL as a modeling language enables a modeler to use a standard VHDL simulator for, timing analysis, test generation, circuit partitioning, and other applications that require special gate or component models.